Fixed-Throughput GRAND with FIFO Scheduling

TL;DR

This work addresses the nondeterministic throughput of GRAND-based decoders by introducing a FIFO-based fixed-throughput architecture. The proposed design uses an input FIFO, an array of decoders, an output ROB, plus a ROB booking mechanism and an early-termination module to preserve data order and sustain constant throughput while exploiting GRAND's variable runtime to improve BLER. Through simulations with a random $(256,234)$ code and ORBGRAND, the authors show that achieving $1\%$ BLER under fixed throughput requires roughly an order of magnitude lower throughput than unconstrained ORBGRAND, and that larger input/output buffers yield BLER gains while adding decoders offers diminishing returns. The study highlights practical design trade-offs among BLER, throughput, latency, and dynamic power for real-time GRAND-based decoders, demonstrating a viable path to deterministic performance in systems with streaming data.

Abstract

Guessing random additive noise decoding (GRAND) is a code-agnostic decoding method that iteratively guesses the noise pattern affecting the received codeword. The number of noise sequences to test depends on the noise realization. Thus, GRAND exhibits random runtime which results in nondeterministic throughput. However, real-time systems must process the incoming data at a fixed rate, necessitating a fixed-throughput decoder in order to avoid losing data. We propose a first-in first-out (FIFO) scheduling architecture that enables a fixed throughput while improving the block error rate (BLER) compared to the common approach of imposing a maximum runtime constraint per received codeword. Moreover, we demonstrate that the average throughput metric of GRAND-based hardware implementations typically provided in the literature can be misleading as one needs to operate at approximately one order of magnitude lower throughput to achieve the BLER of an unconstrained decoder.

Figures (6)

• Figure 1: Average throughput of ORBGRAND to achieve $1\%$ BLER versus maximum constant throughput achieved by hardware design D1 from CJ23 without FIFO scheduling (in red) and with FIFO scheduling (in blue).
• Figure 2: FIFO scheduling architecture overview: a) data source, b) input buffer, c) distribution unit, d) array of decoders, e) collection unit, f) ROB, g) data sink, h) booking mechanism, i) early termination, and j) distribution control.
• Figure 3: (a) Conditions that trigger an early termination (E. T.) and (b) control flow taking place when an early termination is triggered.
• Figure 4: FIFO scheduling with a single decoder, more than one FIFO/ROB slot ($F, R > 1$, $D=1$), $I=4$, and a constant input-output latency of $16$ clock cycles. Each row illustrates a hypothetical data flow through our architecture, showing a constant input-output latency for the $i$th and $(i+1)$th codeword $\boldsymbol{\lambda}^\text{(i)}$ and $\boldsymbol{\lambda}^\text{(i+1)}$, respectively, despite the random decoding time.
• Figure 5: Influence of data parallelism $P$ on BLER in a ($F=R=4$, $D=1$) FIFO scheduling architecture, $I = 10$ clock cycles (a). BLER at different arrival intervals $I$ in a (4,1) configuration and unconstrained (Unc.) ORBGRAND (b). BLER for different FIFO scheduling configurations ($F=R=P$, $D$) (c).