Caribou - A versatile data acquisition system for silicon pixel detector prototyping

TL;DR

The paper addresses the need for a scalable, reusable DAQ platform for silicon pixel detector prototyping across multiple collaborations. It introduces Caribou, a modular architecture combining CaR hardware, a Zynq SoC running embedded Linux, and a unified software/firmware stack (Peary and Boreal) to enable rapid integration and testing of new detector prototypes. Key contributions include hardware upgrades (CaR v1.5), the Boreal firmware framework, and the Peta-Caribou image-building workflow, plus a roadmap to Caribou v2.0 with UltraScale+ SoM integration for full system-on-module functionality. The approach promises reduced development time and cost, with demonstrated deployment across numerous detector prototypes and institutes, enhancing collaboration and scalability in silicon pixel DAQ development.

Abstract

Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared accross different projects, thereby drastically reducing the development effort and cost. It consists of a custom Control and Readout (CaR) board and a commercial Xilinx Zynq System-on-Chip (SoC) platform. The SoC platform runs a full Yocto distribution integrating the custom software framework (Peary) and a custom FPGA firmware built within a common firmware infrastructure (Boreal). The CaR board provides a hardware environment featuring various services such as powering, slow-control, and high-speed data links for the target detector prototype. Boreal and Peary, in turn, offer firmware and software architectures that enable seamless integration of control and readout for new devices. While the first version of the system used a SoC platform based on the ZC706 evaluation board, migration to a Zynq UltraScale+ architecture is progressing towards the support of the ZCU102 board and the ultimate objective of integrating the SoC functionality directly into the CaR board, eliminating the need for separate evaluation boards. This paper describes the Caribou system, focusing on the latest project developments and showcasing progress and future plans across its hardware, firmware, and software components.

Figures (5)

• Figure 1: Hardware components of the Caribou DAQ system
• Figure 2: Simplified block diagram of the Caribou hardware architecture Dannheim
• Figure 3: Mitigation of distortions and ringing affecting the bidirectional level shifters for CMOS signals
• Figure 4: Block design of the H2M Ruiz Daza chip firmware support on the ZC706 board
• Figure 5: Peta-Caribou build and deployment workflow