Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables

TL;DR

This work tackles automatic transistor sizing for operational transconductance amplifiers (OTAs) under stringent performance constraints, addressing the high SPICE cost of traditional optimization loops. It proposes a transformer‑based framework that treats circuit sizing as a language‑translation task on driving‑point signal flow graph (DP‑SFG) sequences, predicting DP‑SFG parameters which are then mapped to transistor widths via precomputed LUTs using the gm/Id methodology. The four‑part workflow—DP‑SFG extraction, transformer prediction, LUT‑based width estimation, and SPICE verification with margin adjustment—delivers substantial speedups, achieving over 90% first‑pass success on unseen specs and requiring only a handful of SPICE verifications for full convergence. The approach reduces SPICE dependency to a one‑time training phase and enables rapid sizing across three OTA topologies (5T‑OTA, CM‑OTA, 2S‑OTA), with end‑to‑end runtimes from seconds to minutes. This work provides a practical, scalable path to automated OTA design within layout flows.

Abstract

Device sizing is crucial for meeting performance specifications in operational transconductance amplifiers (OTAs), and this work proposes an automated sizing framework based on a transformer model. The approach first leverages the driving-point signal flow graph (DP-SFG) to map an OTA circuit and its specifications into transformer-friendly sequential data. A specialized tokenization approach is applied to the sequential data to expedite the training of the transformer on a diverse range of OTA topologies, under multiple specifications. Under specific performance constraints, the trained transformer model is used to accurately predict DP-SFG parameters in the inference phase. The predicted DP-SFG parameters are then translated to transistor sizes using a precomputed look-up table-based approach inspired by the gm/Id methodology. In contrast to previous conventional or machine-learning-based methods, the proposed framework achieves significant improvements in both speed and computational efficiency by reducing the need for expensive SPICE simulations within the optimization loop; instead, almost all SPICE simulations are confined to the one-time training phase. The method is validated on a variety of unseen specifications, and the sizing solution demonstrates over 90% success in meeting specifications with just one SPICE simulation for validation, and 100% success with 3-5 additional SPICE simulations.

Figures (7)

• Figure 1: Architecture of a transformer.
• Figure 2: (a) Schematic and (b) DP-SFG for an active inductor.
• Figure 3: Overall sizing flow using our transformer-based method.
• Figure 4: Input: DP-SFG paths with desired performance specifications, Output: Predicted sequences with device parameter values.
• Figure 5: LUT generation and characterization.