A Methodology for Process Design Kit Re-Centering Using TCAD and Experimental Data for Cryogenic Temperatures

TL;DR

The paper tackles the lack of cryogenic PDKs for CMOS by presenting a TCAD-driven re-centering workflow that uses a minimal set of cryogenic measurements to adapt room-temperature PDKs for operation at 77 K (and 4 K). The method builds a TT TCAD deck from RT PDK data, calibrates it to both RT and cryogenic measurements, and then extracts compact models for TT, SS, and FF corners, including band-tail and mobility effects. A Shifted TT (STT) representation captures process-induced offsets, enabling generation of cryogenic target data and compact-model extraction without dedicated foundry support. The authors discuss limitations of TCAD accuracy at deep cryogenic temperatures and outline future work to incorporate statistical SPICE models and RF/capacitance extensions.

Abstract

In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.

Figures (4)

• Figure 1: Overview of the cryogenic PDK re-centering methodology. The flowchart outlines the sequential steps starting from TCAD structure creation and calibration using room-temperature PDK data, followed by adjustment using measured data from fabricated devices, and culminating in the generation of compact models for cryogenic temperatures. The approach supports TT, SS, and FF corner models and can be extended to include statistical variability. (Corner-specific branches are omitted here for clarity.).
• Figure 2: Comparison of calibrated TCAD derived characteristics of the TT transistor with foundry-provided PDK data at room temperature (T = 300 K): (a) linear ($V_{\rm DS}$=0.05V) (b) saturation ($V_{\rm DS}$=$V_{\rm DD}$). Also shown are the slow-slow (SS) and fast-fast (FF) corner transistors from the room-temperature PDK for reference. Back gate bias, $V_{\rm BG}$=0V. The units used are arbitrary (a.u.).
• Figure 3: (a) Comparison of $I_{\rm DS}-V_{\rm GS}$ characteristics of the TT transistor in Fig. 2 and the corresponding measurement data at T=300K, highlighting the mismatch (b) Comparison and match between the measurement data on a fabricated silicon wafer and the calibrated shifted TCAD model. T=300K. (c) Comparison between the measurement data and the calibrated shifted TCAD model both at cryogenic temperature ($T$=$T_{\rm Cryo}$) at low and high drain biases. $V_{\rm BG}$=0V.
• Figure 4: Comparison between the target $I_{\rm DS}-V_{\rm GS}$ data obtained from TCAD simulation of the original TT transistor at cryogenic temperature and the extracted compact model at low and high drain biases. $V_{\rm BG}$=0V.