Automated tuning and characterization of single-electron and single-hole transistor charge sensors

Abstract

We present an automated protocol for tuning single-electron transistors (SETs) and single-hole transistors (SHTs) to operate as high-sensitivity DC charge sensors. The protocol initializes a previously unmeasured device after cooldown, identifies a working point in barrier-gate space, and selects and ranks charge-sensing operating points. It further automates the acquisition and analysis of Coulomb diamonds to extract sensor-relevant parameters, including lever arm, charging energy, gate and source/drain capacitances, and estimated dot radius. We demonstrate the protocol on accumulation-mode silicon MOS SET and SHT devices operated at 1.5 K and $\approx 50$ mK, respectively, establishing ambipolar applicability across a wide temperature range. Operation at 1.5 K indicates that charge sensing in compact MOS devices is feasible in the 1-2 K regime, supporting higher-temperature readout relevant to scalable spin-qubit architectures. Compared to manual tuning, automation reduces operator overhead and provides consistent device characterization, with clear pathways for further speedups and improved robustness via faster electronics and feedback-based stabilization.

Figures (5)

• Figure 1: (a) Schematic of the experimental setup. The device is held at $T_{cryo}$, which is either 1.5 K in a pumped $^4$He cryostat or $\approx 50$ mK in a dilution refrigerator. The computer, DC voltage source and digital multimeter communicate via GPIB. A Python script (tuner.py) runs the tuning protocol by controlling the voltages supplied to the device gate, source and drain electrodes using an SRS SIM928 voltage source. The data is then acquired from a Keysight 34401A multimeter. The source-drain current is read by a current-voltage preamplifier fed into the digital multimeter. The preamplifier gain (g) is typically set in the range of $10^7-10^8$ V/A. (b) False-color scanning electron micrograph (top view) and (c) schematic cross-section (side view) of the SET device. The Ti/Pd gate electrodes are deposited by electron-beam physical vapor deposition. Separating the barrier gates B1 and B2 from the top accumulation gate A is a 5 nm film of Al$_2$O$_3$ deposited by atomic layer deposition. The conducting channel forms in intrinsic (undoped) silicon, below 10 nm of thermally grown SiO$_2$. The doped (n$^{+}$) Ohmic regions shown in (c) are only schematic; they are far away from the device region in the actual device. The SHT device has a similar structure and geometry, but with p$^{+}$-doped Ohmic contacts.
• Figure 2: Overview of the autotuning protocol demonstrated on the SET at a temperature of 1.5 K. Stage 1 involves global turn-on followed by (a) lowering barrier gate voltages separately to determine their pinch-off curves, which are fitted to a sigmoid function. Source-drain bias is 100 $\mu V$. The output of stage 1, indicated by the blue and orange arrows, is the center position and characteristic width of each sigmoid. The inset illustrates the sigmoidal fit to the B1 pinchoff curve. (b) In stage 2, a 2D current-voltage measurement is performed based on the barrier gate voltage ranges determined in stage 1. The pinch-off region is shown as shaded purple, and is the standard range used when running the protocol, although a 2D sweep over a wider range is shown here for clarity. To choose candidate working points $(V_{\mathrm{B1}},V_{\mathrm{B2}})$ in the sequential tunneling regime, image analysis tools are used to detect Coulomb oscillation features and define a set of 1D current traces along lines perpendicular to these features (indicated by the yellow parallel lines). Up to four current peaks along each of these 1D traces (indicated by stars) are selected as candidate working points.
• Figure 3: Stage 3 of the tuning protocol performed on the SET device at a temperature of 1.5 K. (a) A representative 1D current trace for the SET as a function of the plunger gate voltage, with a source-drain bias of 100 $\mu V$. Each such current trace is taken with the barrier gate voltages set to working points found in Stage 2. Within each trace, the highest sensitivity points are found by computing the corresponding transconductance G. (b) The transconductance corresponding to the 1D current trace in (a). The 4 points with highest transconductance, up to the resolution of the measured trace, are labeled with orange dots.
• Figure 4: Stages 1 and 3 of the tuning protocol performed on the SHT device at $T \approx 50$ mK. (a) Pinch-off curves; the double-sided arrows indicate the widths of the sigmoidal fits in stage 1. (b) Charge sensor operating points found for the SHT in stage 3. The orange dots indicate the four highest sensitivity points in the 1D trace shown.
• Figure 5: Coulomb diamonds for the SET measured at 1.5 K, with detected edges overlaid in solid blue lines. (a) Source-drain current $I_{SD}$ indicated in colorscale, versus the plunger gate voltage ($V_P$) and source-drain voltage ($V_{SD}$). (b) Detected diamond edges plotted over the logarithm of the current.