H-MBR: Hypervisor-level Memory Bandwidth Reservation for Mixed Criticality Systems

TL;DR

This paper addresses memory bandwidth contention in mixed-criticality systems on heterogeneous multicore platforms by introducing H-MBR, a VM-centric memory bandwidth reservation mechanism implemented in the Bao hypervisor. H-MBR assigns per-VM budgets and periods and enforces them via per-vCPU PMU counters and a timer, enabling static, VM-level temporal isolation across diverse OSs (e.g., Linux, RTOS) without requiring hardware-specific changes. The approach demonstrates low overhead for regulated workloads (below 1% for periods $\geq 2\mu s$) and provides clear guidance on how bandwidth can be traded via $Bandwidth = \frac{Budget}{Period}$ to manage interference, with worst-case overhead reaching 14% at $1\mu s$. The findings establish H-MBR as a portable, platform-agnostic solution that improves predictability for critical tasks in embedded MCS, while preserving flexibility and scalability for future extensions such as dynamic adaptation and integration with additional isolation mechanisms.

Abstract

Recent advancements in fields such as automotive and aerospace have driven a growing demand for robust computational resources. Applications that were once designed for basic MCUs are now deployed on highly heterogeneous SoC platforms. While these platforms deliver the necessary computational performance, they also present challenges related to resource sharing and predictability. These challenges are particularly pronounced when consolidating safety and non-safety-critical systems, the so-called Mixed-Criticality Systems (MCS) to adhere to strict SWaP-C requirements. MCS consolidation on shared platforms requires stringent spatial and temporal isolation to comply with functional safety standards. Virtualization, mainly leveraged by hypervisors, is a key technology that ensures spatial isolation across multiple OSes and applications; however, ensuring temporal isolation remains challenging due to contention on shared hardwar resources, which impacts real-time performance and predictability. To mitigate this problem, several strategies as cache coloring and memory bandwidth reservation have been proposed. Although cache coloring is typically implemented on state-of-the-art hypervisors, memory bandwidth reservation approaches are commonly implemented at the Linux kernel level or rely on dedicated hardware and typically do not consider the concept of VMs that can run different OSes. To fill the gap between current memory bandwidth reservation solutions and the deployment of MCSs that operate on a hypervisor, this work introduces H-MBR, an open-source VM-centric memory bandwidth reservation mechanism. H-MBR features (i) VM-centric bandwidth reservation, (ii) OS and platform agnosticism, and (iii) reduced overhead. Empirical results evidenced no overhead on non-regulated workloads, and negligible overhead (<1%) for regulated workloads for regulation periods of 2 us or higher.

Figures (11)

• Figure 1: Mibench Execution Time and Bus Cycles (Ratio)
• Figure 2: System Overview
• Figure 3: Standalone setup with single Linux VM.
• Figure 4: Co-existing setup with two VMs: (i) a Linux VM and (ii) a baremetal VM.
• Figure 5: interf+mbr NC throughput budget variation