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Compact Yet Highly Accurate Printed Classifiers Using Sequential Support Vector Machine Circuits

Ilias Sertaridis, Spyridon Besias, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis

TL;DR

This paper tackles implementing ML classifiers in printed electronics under stringent area and power constraints. It introduces print-ready Bespoke Sequential SVMs that fold the computation of multiple support vectors into a single Multiply-Accumulate engine, aided by memory for model parameters and a compact control unit realized as a binary decision DAG for One-vs-One multiclass. The training pipeline uses fixed-point quantization and automatic Verilog generation to embed model parameters, achieving high accuracy with compact hardware. Empirical results across five datasets show dramatically lower area and power than fully parallel SVMs while maintaining or improving accuracy, outperforming other approximate digital classifiers, and fitting within printed battery budgets. The approach is particularly suited to electrostatically gated PE like EGFET and offers a path to scalable, high-accuracy printed classifiers.

Abstract

Printed Electronics (PE) technology has emerged as a promising alternative to silicon-based computing. It offers attractive properties such as on-demand ultra-low-cost fabrication, mechanical flexibility, and conformality. However, PE are governed by large feature sizes, prohibiting the realization of complex printed Machine Learning (ML) classifiers. Leveraging PE's ultra-low non-recurring engineering and fabrication costs, designers can fully customize hardware to a specific ML model and dataset, significantly reducing circuit complexity. Despite significant advancements, state-of-the-art solutions achieve area efficiency at the expense of considerable accuracy loss. Our work mitigates this by designing area- and power-efficient printed ML classifiers with little to no accuracy degradation. Specifically, we introduce the first sequential Support Vector Machine (SVM) classifiers, exploiting the hardware efficiency of bespoke control and storage units and a single Multiply-Accumulate compute engine. Our SVMs yield on average 6x lower area and 4.6% higher accuracy compared to the printed state of the art.

Compact Yet Highly Accurate Printed Classifiers Using Sequential Support Vector Machine Circuits

TL;DR

This paper tackles implementing ML classifiers in printed electronics under stringent area and power constraints. It introduces print-ready Bespoke Sequential SVMs that fold the computation of multiple support vectors into a single Multiply-Accumulate engine, aided by memory for model parameters and a compact control unit realized as a binary decision DAG for One-vs-One multiclass. The training pipeline uses fixed-point quantization and automatic Verilog generation to embed model parameters, achieving high accuracy with compact hardware. Empirical results across five datasets show dramatically lower area and power than fully parallel SVMs while maintaining or improving accuracy, outperforming other approximate digital classifiers, and fitting within printed battery budgets. The approach is particularly suited to electrostatically gated PE like EGFET and offers a path to scalable, high-accuracy printed classifiers.

Abstract

Printed Electronics (PE) technology has emerged as a promising alternative to silicon-based computing. It offers attractive properties such as on-demand ultra-low-cost fabrication, mechanical flexibility, and conformality. However, PE are governed by large feature sizes, prohibiting the realization of complex printed Machine Learning (ML) classifiers. Leveraging PE's ultra-low non-recurring engineering and fabrication costs, designers can fully customize hardware to a specific ML model and dataset, significantly reducing circuit complexity. Despite significant advancements, state-of-the-art solutions achieve area efficiency at the expense of considerable accuracy loss. Our work mitigates this by designing area- and power-efficient printed ML classifiers with little to no accuracy degradation. Specifically, we introduce the first sequential Support Vector Machine (SVM) classifiers, exploiting the hardware efficiency of bespoke control and storage units and a single Multiply-Accumulate compute engine. Our SVMs yield on average 6x lower area and 4.6% higher accuracy compared to the printed state of the art.

Paper Structure

This paper contains 9 sections, 1 equation, 2 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Printed Bespoke Sequential SVMs
  4. SVM Training
  5. Support Vector Storage
  6. Single MAC Support Vector Engine
  7. Control Unit
  8. Results and Analysis
  9. Conclusion

Figures (2)

  • Figure 1: Overview of our proposed sequential circuits. They consist of three main components memory, SVM compute engine and control unit.
  • Figure 2: Example execution of our sequential . $4$ classes and $6$ input features/weights are considered. Support vectors corresponding to selected nodes are shown on the right, along with the classification output of the support vector engine. The output class is predicted in $3\times 7=21$ cycles. Fixed point values are represented by integers.