Function Approximation Using Analog Building Blocks in Flexible Electronics

TL;DR

This paper tackles function approximation in Flexible Electronics under tight area and power constraints by proposing a systematic analog framework based on Analog Building Blocks (ABBs) to realize splines, which feed into Kolmogorov-Arnold Networks (KANs). The approach yields substantial hardware benefits, achieving approximately $125\\times$ area reduction and $10.59\\%$ power savings over a digital 8-bit spline, with an NMPE that can reach up to $7.58\\%$ due to design and parasitics. It provides a detailed ABB design, a spline implementation optimized for hardware, and a fully analog KAN architecture evaluated against digital baselines, demonstrating the viability of analog computation in FE while acknowledging the need for further error reduction and cost minimization. The work highlights a promising pathway for energy-efficient, compact computation in FE, with future directions including higher-order approximations, co-design strategies, and explorations beyond the voltage domain to extend operating ranges.

Abstract

Function approximation is crucial in Flexible Electronics (FE), where applications demand efficient computational techniques within strict constraints on size, power, and performance. Devices like wearables and compact sensors are constrained by their limited physical dimensions and energy capacity, making traditional digital function approximation challenging and hardware-demanding. This paper addresses function approximation in FE by proposing a systematic and generic approach using a combination of Analog Building Blocks (ABBs) that perform basic mathematical operations such as addition, multiplication, and squaring. These ABBs serve as the foundation for constructing splines, which are then employed in the creation of Kolmogorov-Arnold Networks (KANs), improving the approximation. The analog realization of KAN offers a promising alternative to digital solutions, providing significant hardware benefits, particularly in terms of area and power consumption. Our design achieves a 125x reduction in area and a 10.59% power saving compared to a digital spline with 8-bit precision. Results also show that the analog design introduces an approximation error of up to 7.58% due to both the design and parasitic elements. Nevertheless, KANs are shown to be a viable candidate for function approximation in FE, with potential for further optimization to address the challenges of error reduction and hardware cost.

Figures (7)

• Figure 1: Proposed methodology to build KAN. The basis for KAN is spline which is interpreted by the second order equation.
• Figure 2: Schematic of: a) Inversion b) Subtraction c) Addition d) Multiplication e) Squaring
• Figure 3: Architecture of the spline implementation
• Figure 4: Architecture of the KAN implementation
• Figure 5: Layout of a spline following the architecture presented in \ref{['fig:implementation']}