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DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency

Yuan Zhang, Kuncai Zhong, Jiliang Zhang

TL;DR

This paper addresses the throughput and area-energy efficiency bottlenecks of FPGA-based TRNGs by introducing DH-TRNG, a dynamic hybrid TRNG that fuses jitter- and metastability-based entropy through a dynamic hybrid entropy unit. It employs coupling and feedback strategies and a multistage sampling array to achieve ultra-high throughput with minimal hardware, demonstrating 670 Mbps on Virtex-6 and 620 Mbps on Artix-7 using only 8 slices and sub-0.13 W power, with a throughput metric of $Throughput/(Slices*Power)$ reaching 1139.7. The design passes NIST SP 800-22, NIST SP 800-90B, and AIS-31, and proves robust to PVT variation, indicating strong practical applicability for secure random number generation in encryption systems. The work offers a portable, post-processing-free TRNG solution that can scale across FPGA processes, providing significant impact for trusted execution, blockchain signatures, and edge security applications.

Abstract

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build roots of trust for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. In this work, we propose DH-TRNG, a dynamic hybrid TRNG circuitry architecture with ultra-high throughput and area-energy efficiency. Our DH-TRNG exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, our proposed design has the highest Throughput/SlicesPower with a 2.63 times increase.

DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency

TL;DR

This paper addresses the throughput and area-energy efficiency bottlenecks of FPGA-based TRNGs by introducing DH-TRNG, a dynamic hybrid TRNG that fuses jitter- and metastability-based entropy through a dynamic hybrid entropy unit. It employs coupling and feedback strategies and a multistage sampling array to achieve ultra-high throughput with minimal hardware, demonstrating 670 Mbps on Virtex-6 and 620 Mbps on Artix-7 using only 8 slices and sub-0.13 W power, with a throughput metric of reaching 1139.7. The design passes NIST SP 800-22, NIST SP 800-90B, and AIS-31, and proves robust to PVT variation, indicating strong practical applicability for secure random number generation in encryption systems. The work offers a portable, post-processing-free TRNG solution that can scale across FPGA processes, providing significant impact for trusted execution, blockchain signatures, and edge security applications.

Abstract

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build roots of trust for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. In this work, we propose DH-TRNG, a dynamic hybrid TRNG circuitry architecture with ultra-high throughput and area-energy efficiency. Our DH-TRNG exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, our proposed design has the highest Throughput/SlicesPower with a 2.63 times increase.

Paper Structure

This paper contains 19 sections, 6 equations, 9 figures, 6 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Oscillation Jitter
  4. Sampling Metastability
  5. The Proposed Dynamic Hybrid TRNG
  6. Dynamic Hybrid Entropy Unit
  7. Coupling and Feedback Strategies
  8. Overall Architecture and Area Optimization
  9. Experiment and Results
  10. Randomness Test
  11. NIST SP 800-22 Test
  12. NIST SP 800-90B Test
  13. AIS-31 Test
  14. Restart Test
  15. Deviation Test
  16. ...and 4 more sections

Figures (9)

  • Figure 1: (a) TRNG architecture. (b) Comparison with state-of-the-art TRNGs.
  • Figure 2: (a) Randomness extraction of jitters. (b) Randomness extraction of metastability.
  • Figure 3: (a) Dynamic hybrid unit structure. (b) Randomness extraction principle.
  • Figure 4: (a) Coupling strategy. (b) Feedback strategy.
  • Figure 5: (a) Overall circuitry architecture of DH-TRNG. (b) Implementation with automated placement and routing.
  • ...and 4 more figures