Latch Based Design for Fast Voltage Droop Response

TL;DR

This paper addresses fast voltage droop response in synchronous VLSI by replacing PLL-dependent delay mechanisms with a latch-based, metastability-containing design. The approach combines masking latches, a four-phase phase accumulator, a bespoke delay element, and a pulse shaper to achieve glitch-free clock modulation in response to detected droops, without relying on PLLs. Key contributions include the introduction of differential-sensing masking latches, a metastability-aware timing analysis, and a simple, calibratable droop detector, all demonstrated in an IHP 130 nm implementation targeting around 400 MHz. The work reduces response latency to droops (within two clock cycles) and increases robustness to process, voltage, and temperature variations, with practical implications for energy-efficient, resilient VLSI designs.

Abstract

We present a latch-based and PLL-free design of the voltage droop correction circuit of Lenzen, Fuegger, Kinali, and Wiederhake\cite{DroopJournal}. Such a circuit dynamically modifies the clock frequency of a digital clock for VLSI systems. Our circuit responds within two clock cycles and halves the length of the synchroniser chain compared to the previous design. Further, we introduce a differential sensor based design for masking latches as a replacement for masking flip flops that the design of \cite{DroopJournal} requires, but leaves unspecified. The use of latches instead of threshold-altered flip flops alters the timing properties of our design and thus the proofs of correctness that accompanied their design require modifications which we present here. This design has been successfully implemented on the IHP 130 nm process technology. The results of the experimental measurements will be discussed in a subsequent publication.

Figures (11)

• Figure 1: Frequency Adaptation Module: The high-level schematics are identical to DroopJournal, with the exception that the input frequency is twice the output frequency. This allows to add phase delay to the output clock of default period $T=50$ ns in increments of $T/4$ without needing accurate delays within the phase accumulator implementation. The phase accumulator decides in each clock cycle whether to delay the next rising clock transition by $T/4$ based on the binary input G_IN. The delay elements form a synchronizer chain ensuring that the droop_detected signal, which is sampled with each element's output clock, exposes the phase accumulator to a negligible probability of setup/hold time violations only. However, the delay elements simultaneously serve the purpose of immediately adding a phase shift of $T/4$ whenever the droop_detected signal is stable $1$ upon being sampled. This requires a careful design of the delay element that guarantees a glitch-free clock signal with feasible timing even when the delay element suffers from metastability due to sampling a non-stable value at E_IN.
• Figure 2: Masking latch. The latch provides a $0$-masking output, i.e., it implements an Mask-0_Latch
• Figure 3: Masking latch that provides both a $0$- and a $1$-masking output, i.e., it implements both Mask-0 Latch and Mask-1_Latch.
• Figure 4: Synchronizer latch metastability analysis result plots.
• Figure 5: Mask-0 latch metastability analysis result plots.

Theorems & Definitions (4)

• Theorem 2.1
• proof : Proof Sketch
• Theorem 2.2
• proof : Proof Sketch