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Efficient Stochastic Polar Decoder With Correlated Stochastic Computing

Jiaxing Li, Shuwen Zhang, Zhisong Bie

TL;DR

The paper tackles the challenge of efficiently decoding polar codes with hardware-friendly stochastic methods by addressing correlation-induced hold-state. It introduces the Efficient Correlated Stochastic Polar Decoder (ECS-PD), operating in the $LLR$ domain and powered by a unidirectional computing unit and a probability tracker to couple iterations with computation. Two optimization strategies reduce iterations by up to $25.2\%$ at $E_b/N_0=3$ dB and significantly cut circuit area, yielding throughput up to $3816.5$ Mb/s at $1625$ MHz and hardware efficiency of $25{,}614$ Mb/s/mm$^2$ at $E_b/N_0=3.5$ dB, about $2.7\times$ more efficient than the min-sum decoder. The design uses frozen-bit graph simplifications and CRC-based early termination to deliver practical performance with high area efficiency on a $28$-nm ASIC implementation.

Abstract

Polar codes have gained significant attention in channel coding for their ability to approach the capacity of binary input discrete memoryless channels (B-DMCs), thanks to their reliability and efficiency in transmission. However, existing decoders often struggle to balance hardware area and performance. Stochastic computing offers a way to simplify circuits, and previous work has implemented decoding using this approach. A common issue with these methods is performance degradation caused by the introduction of correlation. This paper presents an Efficient Correlated Stochastic Polar Decoder (ECS-PD) that fundamentally addresses the issue of the `hold-state', preventing it from increasing as correlation computation progresses. We propose two optimization strategies aimed at reducing iteration latency, increasing throughput, and simplifying the circuit to improve hardware efficiency. The optimization can reduce the number of iterations by 25.2% at $E_b/N_0$ = 3 dB. Compared to other efficient designs, the proposed ECS-PD achieves higher throughput and is 2.7 times more hardware-efficient than the min-sum decoder.

Efficient Stochastic Polar Decoder With Correlated Stochastic Computing

TL;DR

The paper tackles the challenge of efficiently decoding polar codes with hardware-friendly stochastic methods by addressing correlation-induced hold-state. It introduces the Efficient Correlated Stochastic Polar Decoder (ECS-PD), operating in the domain and powered by a unidirectional computing unit and a probability tracker to couple iterations with computation. Two optimization strategies reduce iterations by up to at dB and significantly cut circuit area, yielding throughput up to Mb/s at MHz and hardware efficiency of Mb/s/mm at dB, about more efficient than the min-sum decoder. The design uses frozen-bit graph simplifications and CRC-based early termination to deliver practical performance with high area efficiency on a -nm ASIC implementation.

Abstract

Polar codes have gained significant attention in channel coding for their ability to approach the capacity of binary input discrete memoryless channels (B-DMCs), thanks to their reliability and efficiency in transmission. However, existing decoders often struggle to balance hardware area and performance. Stochastic computing offers a way to simplify circuits, and previous work has implemented decoding using this approach. A common issue with these methods is performance degradation caused by the introduction of correlation. This paper presents an Efficient Correlated Stochastic Polar Decoder (ECS-PD) that fundamentally addresses the issue of the `hold-state', preventing it from increasing as correlation computation progresses. We propose two optimization strategies aimed at reducing iteration latency, increasing throughput, and simplifying the circuit to improve hardware efficiency. The optimization can reduce the number of iterations by 25.2% at = 3 dB. Compared to other efficient designs, the proposed ECS-PD achieves higher throughput and is 2.7 times more hardware-efficient than the min-sum decoder.

Paper Structure

This paper contains 13 sections, 8 equations, 6 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Polar Decoding Algorithm And Stochastic Computing
  3. Polar Codes
  4. Belief Propagation Based Decoding of Polar Codes
  5. Stochastis Computing
  6. Correlated Stochastic Decoder
  7. Computing Unit
  8. Frozen Factor Graph
  9. Hardware Implementation And Performance Evaluation
  10. The Structure Of ECS-PD
  11. Performance Evaluation
  12. Hardware Implementation
  13. Conclusion

Figures (6)

  • Figure 1: AND gate function in different SCC. (a) SCC=0; (b) SCC=+1.
  • Figure 2: The structure of (a) computing units; (b) $F$ function module; (c) $G$ function module; (d) probability tracker.
  • Figure 3: Factor graph with $N=8$ and CU type simplified based on frozen bits.
  • Figure 4: The structure of simplified CUs. Type $\mathrm{I}$: both $R_{i,j}$ and $R_{i,j+N/2}$ are frozen bits; Type $\mathrm{II}$: $R_{i,j}$ is frozen bits; Type $\mathrm{III}$: $R_{i,j+N/2}$ is frozen bits.
  • Figure 5: The architecture of ECS-PD.
  • ...and 1 more figures