Ion-Trap Chip Architecture Optimized for Implementation of Quantum Error-Correcting Code

TL;DR

The paper tackles scalable fault-tolerant quantum computation with trapped ions by introducing a chip architecture that uses orthogonal horizontal and vertical connectivity to support transversal and non-transversal gates plus syndrome extraction under a 2D color code. It combines a dedicated transpiler, scheduler, and error analyzer to demonstrate that increasing the color-code distance by two substantially reduces the effective logical two-qubit gate error to around $p_{2Q}^{*} \sim 10^{-7}$–$10^{-8}$ when using a $[[31,1,7]]$ code, enabling reliable execution of large circuits. Although QEC introduces runtime overhead from error-correction cycles and shuttling, the results show improved success probabilities for benchmarks and the potential to scale to thousands of logical qubits depending on the algorithm. The work provides a practical, hardware-conscious pathway from the NISQ era to fault-tolerant trapped-ion quantum computing, with clear directions for further optimization and integration of sympathetic cooling.

Abstract

We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to non-transversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as $10^{-8}$ with the $[[31, 1, 7]]$ color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.

Figures (11)

• Figure 1: Orthogonal connectivity requirements for transversal versus non-transversal gates and syndrome extraction. For the case of the $[[7, 1, 3]]$ code, each logical qubit is encoded using seven physical qubits. Transversal two-qubit gates require the qubit connectivity represented by the horizontal lines. In contrast, non-transversal gates and syndrome extraction require interactions with auxiliary qubits, represented by the vertical double line.
• Figure 2: Configuration of the proposed chip layout featuring horizontal trap regions (H-trap regions) and vertical sectors (V sectors) to support diverse qubit-connectivity requirements, with parameters $n=7,C=5, N=8, L=3$, and $L_e=1$. $n$ H-trap regions, each containing a chain of $C$ ions, are arranged in parallel to form a horizontal sector (H sector). V sectors are placed between H sectors and connected to the auxiliary-qubit module. Note that RF electrodes are omitted for clarity, and the figure is not to scale; the actual sizes, numbers, and shapes of components, including ions and electrodes, will differ in practice. Sets of electrodes that share a common voltage are co-wired and shown in the same color; for clarity, not all such sets are displayed.
• Figure 3: Ion configurations at time step $t$ and $t+1$ during right-shuttling phase. The figure is drawn with parameters $n=7,C=5, N=8, L=3$, and $L_e=1$.
• Figure 4: Flow of stages in the software tool, consisting of three main stages: the transpiler, the scheduler, and the error analyzer.
• Figure 5: Chip models assumed by the scheduler. (a) The model of the proposed chip, where each H sector is represented by a horizontal chain of logical qubits ($C=5$) and each V sector is represented as a single logical qubit. (b) The model of linearly concatenated chains for simulation without a QEC code.