Dynamic Loop Fusion in High-Level Synthesis

TL;DR

This paper tackles the bottleneck of parallelizing irregular memory-access patterns in high-level synthesis by introducing dynamic loop fusion across sibling loops. It proposes a compiler/hardware co-design that relies on a program-order schedule and a monotonic address analysis to enable dynamic memory disambiguation without sequentializing loops or maintaining extensive address histories. Key contributions include a compiler pass to decouple loops into processing elements, a decoupled access/execute architecture with an Address Generation Unit and a Data Unit for hazard detection, and a schedule mechanism that supports non-monotonic outer loops. Evaluations on ten irregular benchmarks show substantial speedups—averaging 14× over static HLS and 4× over existing dynamic HLS—and reveal area-frequency tradeoffs driven by hazard-pruning and store-to-load forwarding. The work enables finer-grained parallelism in irregular codes and improves DRAM bandwidth utilization through dynamic coalescing and forwarding, with practical implications for FPGA-based accelerators.

Abstract

Dynamic High-Level Synthesis (HLS) uses additional hardware to perform memory disambiguation at runtime, increasing loop throughput in irregular codes compared to static HLS. However, most irregular codes consist of multiple sibling loops, which currently have to be executed sequentially by all HLS tools. Static HLS performs loop fusion only on regular codes, while dynamic HLS relies on loops with dependencies to run to completion before the next loop starts. We present dynamic loop fusion for HLS, a compiler/hardware co-design approach that enables multiple loops to run in parallel, even if they contain unpredictable memory dependencies. Our only requirement is that memory addresses are monotonically non-decreasing in inner loops. We present a novel program-order schedule for HLS, inspired by polyhedral compilers, that together with our address monotonicity analysis enables dynamic memory disambiguation that does not require searching of address histories and sequential loop execution. Our evaluation shows an average speedup of 14$\times$ over static and 4$\times$ over dynamic HLS.

Figures (8)

• Figure 1: Dynamic Loop Fusion enables fine-grained parallelism across loops with memory dependencies.
• Figure 2: An example DAE streaming FPGA architecture.
• Figure 3: Example decoupling of a loop forest. A leaf loop is decoupled into its own PE, which includes loop control of the outer loops. Parent loop body instructions are included only if they come before the leaf loop in the topological order. FIFOs are used to communicate scalar data dependencies (e.g. from loop 1.1.1 in PE 0 to loop 1.1.2 in PE 1). FIFOs are written in the loop exit block and read in the loop pre-header block. Each loop PE might have an AGU producing memory requests fo the accesses in that loop PE.
• Figure 4: Data Unit (DU) consisting of of $n$ Load Store Units.
• Figure 5: Result of pruning hazard pairs in the later evaluated FFT code. Each memory operation checks for safety against at most one operation per loop depth (e.g., $ld_0$ checks against $st_3$ in its first loop depth, and against $st_1$ in the second).