$SpikePack$: Enhanced Information Flow in Spiking Neural Networks with High Hardware Compatibility

TL;DR

SpikePack addresses core bottlenecks in Spiking Neural Networks by mitigating information loss from pre- to post-synaptic spikes and by enabling time-parallel computation on modern hardware. It introduces a global membrane potential $v_g^l$ and a spike-compression pipeline that yield $\mathcal{O}(1)$ time and space complexity, while preserving key neural dynamics and enabling near-lossless ANN-to-SNN conversion. Across ImageNet-class classification, COCO object detection, and ADE20K semantic segmentation, SpikePack achieves higher accuracy at comparable or lower computational cost than state-of-the-art SNNs and neuron designs, with robust cross-platform hardware validation on FPGA. The work provides a unified framework combining improved information flow, efficient gradient propagation, and strong ANN compatibility, accelerating practical deployment of SNNs on diverse hardware ecosystems.

Abstract

Spiking Neural Networks (SNNs) hold promise for energy-efficient, biologically inspired computing. We identify substantial informatio loss during spike transmission, linked to temporal dependencies in traditional Leaky Integrate-and-Fire (LIF) neuron-a key factor potentially limiting SNN performance. Existing SNN architectures also underutilize modern GPUs, constrained by single-bit spike storage and isolated weight-spike operations that restrict computational efficiency. We introduce ${SpikePack}$, a neuron model designed to reduce transmission loss while preserving essential features like membrane potential reset and leaky integration. ${SpikePack}$ achieves constant $\mathcal{O}(1)$ time and space complexity, enabling efficient parallel processing on GPUs and also supporting serial inference on existing SNN hardware accelerators. Compatible with standard Artificial Neural Network (ANN) architectures, ${SpikePack}$ facilitates near-lossless ANN-to-SNN conversion across various networks. Experimental results on tasks such as image classification, detection, and segmentation show ${SpikePack}$ achieves significant gains in accuracy and efficiency for both directly trained and converted SNNs over state-of-the-art models. Tests on FPGA-based platforms further confirm cross-platform flexibility, delivering high performance and enhanced sparsity. By enhancing information flow and rethinking SNN-ANN integration, ${SpikePack}$ advances efficient SNN deployment across diverse hardware platforms.

Figures (9)

• Figure 1: Performance of SpikePack on Spikeformer-8-512 across different time steps (T), showing error rate (%), time (ep/min), and memory (MB/img). Reference model uses LIF neurons (Ref, T=4).
• Figure 2: Forward and backward computation in SpikePack, showing both serial and parallel modes. Parallel computation uses $s_{\text{zip}}^l$ for efficient global potential ($v_g^l$) calculation.
• Figure 3: Spike sequence compression into integer $s_{\text{zip}}^l$ for efficient computation of $v_g^l$ without decompression.
• Figure 4: Empirical comparison of mutual information between SpikePack and LIF neurons over varying $T$ (time steps) and $N$ (pre-synaptic neurons). SpikePack demonstrates higher information retention across configurations.
• Figure 5: Comparison between SpikePack and other neuron models at different time steps on ImageNet 1k. Our method achieves higher accuracy with lower computational cost.