Connectivity-aware Synthesis of Quantum Algorithms

TL;DR

The paper develops a connectivity-aware framework for synthesizing quantum algorithms using Parity Twine chains and parity-label tracking to efficiently implement logical multi-qubit operators. By building k-body generator circuits on various connectivities (LNN, square grids, ladders, heavy hex, all-to-all), it achieves near-optimal asymptotic gate counts ($\mu$) and controlled depths ($\nu$), with explicit constructions for two-, three-, and higher-body operators. The approach yields substantial improvements for QAOA, QFT, and Hamiltonian simulation across hardware topologies and shows practical performance gains in simulations and on noisy quantum hardware, including real-device experiments. This methodology reveals that moderate connectivity can dramatically reduce resource requirements and provides a scalable path toward quantum advantage with realistic architectures.

Abstract

We present a general method for the implementation of quantum algorithms that optimizes both gate count and circuit depth. Our approach introduces connectivity-adapted CNOT-based building blocks called Parity Twine chains. It outperforms all known state-of-the art methods for implementing prominent quantum algorithms such as the quantum Fourier transform or the Quantum Approximate Optimization Algorithm across a wide range of quantum hardware, including linear, square-grid, hexagonal, ladder and all-to-all connected devices. We show that even moderate increments in connectivity can yield significant efficiency improvements and reach the proven optimum for specific cases. Furthermore, we demonstrate a practical performance advantage of this approach for a wide range of compilation problems and quantum hardware.

Figures (27)

• Figure 1: The average asymptotic gate count as a function of connectivity ranging from linear nearest neighbor, square grid, heavy hexagon, ladder to all-to-all for algorithms considered in this work. The depicted Parity Twine chain constitute basic building blocks used throughout the article. The resulting average gate counts per interaction are schematically indicated as a function of the qubit layout connectivity. Connectivity gains lead to significant reductions in gate count approaching the theoretical optimum for all-to-all connected devices.
• Figure 2: (a) Schematic of a DCNOT gate. (b) Concatenations of DCNOT gates forming a Parity Twine chain. (c) Concatenated Parity Twine chains acting on a decreasing number of qubits and forming the Parity Twine network $\mathrm{PTN}^{(n)}$, generating all possible two-body terms.
• Figure 3: (a) An initialization circuit preparing the input label set for special three-body generators. (b) Schematic of the special three-body generator circuit $\mathrm{PTN}_3^{(n)}$ for the special label $\ell_s$. (c) Schematic of a three-body generator circuit $\mathcal{G}_3^{(n)}$ composed of special three-body generators $\mathrm{PTN}_3^{(n)}$ and $\overline{\mathrm{PTN}}_3^{(n)}$, respectively.
• Figure 4: (a) Schematic of the clean special four-body generator $\mathcal{SG}_4^{(n)}$. (b) Schematic of the four-body generator circuit $\mathcal{G}_4^{(n)}$ from the clean special four-body generator $\mathcal{SG}_4^{(n)}$. (c) Design of a clean special $k$-body generator $\mathcal{SG}_k^{(n)}$ from the clean special $(k\!-\!1)$-body generator $\mathcal{SG}_{k-1}^{(n)}$. We indicate a SWAP gate by crossed-out qubits connected by a line.
• Figure 5: Average count $\mu_n(\mathcal{G}_k^{(n)}, \mathcal{L}_k^{(n)})$ and normalized depth $\nu_n(\mathcal{G}_k^{(n)}, \mathcal{L}_k^{(n)})$ for different $k$-body generator circuits on LNN devices as a function of the number of qubits $n$.

Theorems & Definitions (53)

• Definition A.1: CNOT gate
• Definition A.2: Circuit
• Definition A.3: Reversed CNOT circuit
• Example A.4
• Definition A.5: Adjoint circuit
• Definition A.6: Shifted concatenation of circuits
• Definition A.7: Parity label
• Definition A.8: Label action
• Remark A.9
• Definition A.10: Label generator