Fast-Locking and High-Resolution Mixed-Mode DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS

TL;DR

This paper tackles the challenge of achieving ultra-wide frequency range DLLs with fast, deterministic locking and high timing precision. It introduces a mixed-mode DLL that uses binary-search locking to reduce locking time to $T_{Lock}\approx (B+1)/f_{clkctrl}$, where $B=10$, across 533~MHz to 4.26~GHz, and couples it with a toggle detector to recover from potential clock-failure events without restarting. Implemented in a 3-nm FinFET process, the design delivers sub-ps resolution ($\Delta\phi_{LSB}$ around $0.73$~ps), low jitter (RMS $\approx 1.2$~ps), and favorable figures of merit ($FOM_P=0.82$~pJ and $FOM_{LR}=0.01$~pJ·ns$^2$), while consuming 5.4~mW at 4.26~GHz. The combination of fast locking, high resolution, and robust clock-failure recovery makes the MM-DLL well suited for high-performance parallel interfaces such as DDR and D2D links in modern SoCs.

Abstract

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS) locking, designed to cover a broad frequency range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the binary search controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed MM-DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75 V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed MM-DLL achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking FoM of 0.01 $pJ\cdot ns^2$.

Figures (17)

• Figure 1: Block diagram of a generic MM-DLL.
• Figure 2: Proposed mixed-mode DLL architecture. (a) Block diagram of MM-DLL with binary search control in the digital loop and toggle detector. (b) Schematic diagram of the implemented voltage-controlled delay line (VCDL).
• Figure 3: Schematic diagram of (a) the pseudo-differential delay element (DE) within the VCDL, and (b) the pseudo-differential current-starved inverter (CSI).
• Figure 4: Locking algorithms example. (a) Coarse-fine scheme. (b) BS scheme.
• Figure 5: Simulation of the coarse-fine locking scheme for different PVT conditions. Change in $\Delta T$ for $f_{clkin}$ of (a) 800 MHz and (b) 4.26 GHz, at nominal (blue), fast (red), and slow (black) corners.