Paradigm-Based Automatic HDL Code Generation Using LLMs

TL;DR

This work tackles hallucination and correctness in LLM-generated HDL code from natural language specifications. It introduces paradigm blocks (SEQU, COMB, BEHAV) plus a two-phase workflow that decomposes tasks, classifies circuit type, and reuses intermediate results to reduce errors without fine-tuning. The approach leverages explicit information extraction to produce IO relationships and formats compatible with EDA tools, augmented by fail-safe and shortcut mechanisms. Experimental results on VerilogEval-human/machine demonstrate notable improvements in functional correctness (Pass@k metrics) across GPT-4 variants, validating the effectiveness of paradigm-based generation and intermediate-state reuse for HDL design tasks.

Abstract

While large language models (LLMs) have demonstrated the ability to generate hardware description language (HDL) code for digital circuits, they still face the hallucination problem, which can result in the generation of incorrect HDL code or misinterpretation of specifications. In this work, we introduce a human-expert-inspired method to mitigate the hallucination of LLMs and enhance their performance in HDL code generation. We begin by constructing specialized paradigm blocks that consist of several steps designed to divide and conquer generation tasks, mirroring the design methodology of human experts. These steps include information extraction, human-like design flows, and the integration of external tools. LLMs are then instructed to classify the type of circuit in order to match it with the appropriate paradigm block and execute the block to generate the HDL codes. Additionally, we propose a two-phase workflow for multi-round generation, aimed at effectively improving the testbench pass rate of the generated HDL codes within a limited number of generation and verification rounds. Experimental results demonstrate that our method significantly enhances the functional correctness of the generated Verilog code

Figures (11)

• Figure 1: Comparison of Training-Free Methods: naïve generation, human-aided generation, and RAG generation are illustrated in (a), (b), and (c). By introducing the human-expert-inspired procedure, the proposed method illustrated in (d) enhances the performance of LLM code generation without the need for human labor or a database.
• Figure 2: The proposed paradigm blocks SEQU, COMB, and BEHAV are illustrated in (a), (b), and (c), respectively. The overall procedure is outlined in (d). Solid arrows represent prompts to the LLMs, while the dashed arrow indicates the execution of PyEDA.
• Figure 3: Example of information list generated by LLMs for a sequential logic task. Some LLM responses are omitted due to space constraints.
• Figure 4: Example of information list generated by LLMs for a combinational logic task. Some LLM responses are omitted due to space constraints.
• Figure 5: Example of the state-transition table generated by LLM for a sequential logic.