Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction

TL;DR

This work introduces a position graph abstraction to unify the compilation of shuttling-based trapped-ion quantum computers (QCCD TI) with superconducting-inspired mapping methods. It presents SHuttling-Aware PERmutative search (SHAPER), a block-based, permutation-aware scheduling algorithm that uses a distance graph and a cost function H=F+E to minimize both shuttling overhead and congestion, enabling execution on 2D QCCD layouts. By porting state-of-the-art mapping ideas to the position graph, SHAPER resolves congestion and deadlocks that challenge prior tools and demonstrates compilation for circuits up to mn qubits, outperforming existing methods in many scenarios. The approach is backed by a detailed evaluation across multiple circuits and architectures, showing substantial reductions in shuttling time and highlighting scalable opportunities through graph-based planning and deadlock avoidance techniques.

Abstract

With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial factor in deciding the success of the implementation. There has been rich research and development in compilation techniques for the superconducting-qubit regime. In contrast, the trapped-ion architectures, currently leading in robust quantum computations due to their reliable operations, do not have many competitive compilation strategies. This work presents a novel unifying abstraction, called the position graph, for different types of hardware architectures. Using this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures and enable high-quality, scalable superconducting compilation methods. In particular, we devise a scheduling algorithm called SHuttling-Aware PERmutative heuristic search algorithm (SHAPER) to tackle the complex constraints and dynamics of trapped-ion QCCD with the cooperation of state-of-the-art permutation-aware mapping. This approach generates native, executable circuits and ion instructions on the hardware that adheres to the physical constraints of shuttling-based quantum computers. Using the position graph abstraction, we evaluate our algorithm on theorized and actual architectures. Our algorithm can successfully compile programs for these architectures where other state-of-the-art algorithms fail. In the cases when other algorithms complete, our algorithm produces a schedule that is $14\%$ faster on average, up to $69\%$ in the best case.\\ {\bf Reproducibility:} source code and computational results are available at $[$will be added upon acceptance$]$

Figures (7)

• Figure 1: The H-type murali2020architectingkielpinski2002architecture QCCD-based trapped-ion architecture. Here the ion is moved from one trap to another trap using 3 shuttling operations. Move $(0 \rightarrow 1)$ denotes a split operation to split the ion from the trap. Move $(1 \rightarrow 2)$ and $(2 \rightarrow 3)$ denotes move through Y-junction (T-junction) into segment space. Finally, move $(3 \rightarrow 4)$ shows the merge operation of the ion into the new trap.
• Figure 2: An example of circuit compilation with and without position graph.
• Figure 3: An example of congestion created when trying to move $q_2$ to the same trap with $q_3$. Here, after moving $q_2$ next to the trap containing $q_3$, the merge operation fails due to not enough free space in the trap. The congestion is created as $q_3$ can not be merged into the trap and there is no one-step shuttling operation to free space on the $q_3$ trap.
• Figure 4: Example of mapping a QCCD-based TI architecture to its corresponding position graph. Here, each position in the shuttling paths is mapped to an orange node of the graph, while each available space in a trap, according to the trap's capacity, is also mapped to a node in the position graph. The edges of the position graph are labeled with a shuttling operation such as split, merge, move, and inner swap between ions inside the same trap. When a node is filled (colored purple), it indicates the existence of an ion in that specific space.
• Figure 5: Mapping physical junction to its position graph abstraction. The figure shows how the Y-junction (T-junction), X-junction, and combination of Y-junction (T-junction) are transformed into abstraction.

Theorems & Definitions (1)

• Definition 1: Position Graph