SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design

TL;DR

SkyByte tackles the core bottlenecks of CXL-based SSDs in memory-semantic deployments by co-designing the host OS and the SSD controller. Its coordinated context-switch mechanism hides long flash delays, while the DRAM is reorganized into a cacheline write log and a page-level cache to bridge the CXL byte granularity with flash page granularity; adaptive page migration leverages host memory to extend SSD DRAM. Empirical evaluation in a cycle-accurate simulator shows SkyByte achieving an average 6.11x speedup over state-of-the-art CXL-SSDs, with a 23x reduction in flash I/O traffic and reaching up to 75% of an ideal DRAM-only baseline. These results demonstrate a practical, cost-effective path to scaling memory capacity using CXL-SSDs without resorting to large host DRAM budgets.

Abstract

The CXL-based solid-state drive (CXL-SSD) provides a promising approach towards scaling the main memory capacity at low cost. However, the CXL-SSD faces performance challenges due to the long flash access latency and unpredictable events such as garbage collection in the SSD device, stalling the host processor and wasting compute cycles. Although the CXL interface enables the byte-granular data access to the SSD, accessing flash chips is still at page granularity due to physical limitations. The mismatch of access granularity causes significant unnecessary I/O traffic to flash chips, worsening the suboptimal end-to-end data access performance. In this paper, we present SkyByte, an efficient CXL-based SSD that employs a holistic approach to address the aforementioned challenges by co-designing the host operating system (OS) and SSD controller. To alleviate the long memory stall when accessing the CXL-SSD, SkyByte revisits the OS context switch mechanism and enables opportunistic context switches upon the detection of long access delays. To accommodate byte-granular data accesses, SkyByte architects the internal DRAM of the SSD controller into a cacheline-level write log and a page-level data cache, and enables data coalescing upon log cleaning to reduce the I/O traffic to flash chips. SkyByte also employs optimization techniques that include adaptive page migration for exploring the performance benefits of fast host memory by promoting hot pages in CXL-SSD to the host. We implement SkyByte with a CXL-SSD simulator and evaluate its efficiency with various data-intensive applications. Our experiments show that SkyByte outperforms current CXL-based SSD by 6.11X, and reduces the I/O traffic to flash chips by 23.08X on average. SkyByte also reaches 75% of the performance of the ideal case that assumes unlimited DRAM capacity in the host, which offers an attractive cost-effective solution.

Figures (23)

• Figure 1: System architecture of CXL-based SSD (CXL-SSD).
• Figure 2: End-to-end execution time of running different workloads using DRAM vs. CXL-SSD.
• Figure 3: Latency distribution of DRAM vs. CXL-SSD.
• Figure 4: Execution boundedness breakdown of various workloads with DRAM vs. CXL-SSD.
• Figure 5: Locality distribution of all pages read from flash chips into the SSD DRAM cache. The legend "1:n" means the workload's memory footprint is n$\times$ larger than the SSD DRAM cache. The y-axis is the percentage of cache lines accessed in each page.