A scalable event-driven spatiotemporal feature extraction circuit

TL;DR

The paper addresses the need for low-latency, energy-efficient processing of sparse event streams by developing a robust Time Difference Encoder (TDE) implemented in subthreshold CMOS. The proposed design uses FAC and TRG integrator blocks to form a synapse that generates an exponentially decaying current with an initial magnitude proportional to $e^{-Δt}$, which a neuron converts into spikes that encode the input time difference $Δt$. It demonstrates a substantial robustness improvement over prior work, with Monte Carlo simulations showing a 61% reduction in the coefficient of variation of transmitted charge across Δt, and validates the approach with a silicon-verified 180 nm implementation. An optical flow task using synthetic event data shows the circuit can produce directionally selective responses, illustrating its potential for scalable, real-time edge sensing in neuromorphic systems.

Abstract

Event-driven sensors, which produce data only when there is a change in the input signal, are increasingly used in applications that require low-latency and low-power real-time sensing, such as robotics and edge devices. To fully achieve the latency and power advantages on offer however, similarly event-driven data processing methods are required. A promising solution is the TDE: an event-based processing element which encodes the time difference between events on different channels into an output event stream. In this work we introduce a novel TDE implementation on CMOS. The circuit is robust to device mismatch and allows the linear integration of input events. This is crucial for enabling a high-density implementation of many TDEs on the same die, and for realising real-time parallel processing of the high-event-rate data produced by event-driven sensors.

Figures (7)

• Figure 1: Photograph of the realised "cognigr1" , fabricated in the XFAB 180 technology. The boxes highlight the location of the structures on the die. The total size of the circuit is 19$\times$56 including guard rings.
• Figure 2: The circuit schematics of the synapse. The circuit initially proposed in milde18_doi consists of a single discharge branch in the facilitatory block and a Bartolozzi_Indiveri07b in the trigger block. The improved circuit presented in this work makes use of a circuit in both blocks to ensure linear integration of events. Modifications with respect to the old circuit are highlighted.
• Figure 3: Silicon measurements of the circuit. The received two sequential FAC and TRG input events with a time difference of 12ms. The response of the trigger block, $V_{\text{TRG}}$, generates an through transistor $\text{M}_{10}$ which is integrated by the neuron, eliciting a spiking response observed through the membrane potential $V_{\text{mem}}$.
• Figure 4: Left: Simulated event-based camera data of a textured surface moving in a vertical direction. Center: The x-y space was randomly and sparsely sampled by 100 with an equal ratio of cardinal orientations. Right: Arrows represent the connectivity of FAC and TRG circuit inputs to neighbouring event-based camera pixels.
• Figure 5: Monte Carlo simulation results comparing our circuit with milde18_doi. For a given time difference, $\Delta t$, the charge transmitted by the synapse was measured for 2000 simulated instances of the circuit. This charge was then normalized relative to the average charge for a given $\Delta t$.