Hybrid Parallel Collaborative Simulation Framework Integrating Device Physics with Circuit Dynamics for PDAE-Modeled Power Electronic Equipment

TL;DR

The paper tackles the challenge of accurately simulating power electronic equipment by uniting device-scale PDE physics with circuit-level dynamics within a PDAE framework. It introduces a dynamic-iteration Gauss-Seidel decoupling and a hybrid-parallel computing strategy with physics-based partitioning to accelerate simulations, enabling concurrent resolution of hundreds of PDE-modeled devices. Key contributions include drift-diffusion PDE devices discretized by Scharfetter-Gummel, an equivalent-conductance representation for device-circuit coupling, and a scalable co-simulation workflow that dramatically speeds up high-fidelity analyses. Demonstrations on H-LCC/RB-IGCT topologies show up to 60× speedups over commercial TCAD and strong agreement with experiments, highlighting the approach’s potential for DoEs, design optimization, and failure analysis under extreme conditions.

Abstract

Optimizing high-performance power electronic equipment, such as power converters, requires multiscale simulations that incorporate the physics of power semiconductor devices and the dynamics of other circuit components, especially in conducting Design of Experiments (DoEs), defining the safe operating area of devices, and analyzing failures related to semiconductor devices. However, current methodologies either overlook the intricacies of device physics or do not achieve satisfactory computational speeds. To bridge this gap, this paper proposes a Hybrid-Parallel Collaborative (HPC) framework specifically designed to analyze the Partial Differential Algebraic Equation (PDAE) modeled power electronic equipment, integrating the device physics and circuit dynamics. The HPC framework employs a dynamic iteration to tackle the challenges inherent in solving the coupled nonlinear PDAE system, and utilizes a hybrid-parallel computing strategy to reduce computing time. Physics-based system partitioning along with hybrid-process-thread parallelization on shared and distributed memory are employed, facilitating the simulation of hundreds of partial differential equations (PDEs)-modeled devices simultaneously without compromising speed. Experiments based on the hybrid line commutated converter and reverse-blocking integrated gate-commutated thyristors are conducted under 3 typical real-world scenarios: semiconductor device optimization for the converter; converter design optimization; and device failure analysis. The HPC framework delivers simulation speed up to 60 times faster than the leading commercial software, while maintaining carrier-level accuracy in the experiments. This shows great potential for comprehensive analysis and collaborative optimization of devices and electronic power equipment, particularly in extreme conditions and failure scenarios.

Figures (22)

• Figure 1: Overview of the proposed HPC framework.
• Figure 2: Finite volume Scharfetter-Gummel discretization for the device model, where the mesh is simplified or coarsened only for illustration purpose.
• Figure 3: Flowchart of the Gauss-Seidel type iteration.
• Figure 4: Circuit perspective for Gauss-Siedel type dynamic iteration. Left: PDE-modeled device. Right: Equivalent subsystem derived from implicit derivative.
• Figure 5: A simplified illustration of a converter with 3 levels of equivalent subsystems from a circuit perspective.