Optimizing compilation of error correction codes for 2xN quantum dot arrays and its NP-hardness

TL;DR

This work tackles the practical problem of minimizing qubit shuttling in a $2 \times n$ quantum dot architecture when compiling CSS syndrome-extraction circuits. It introduces gate shuffling and ancilla re-indexing as core optimization levers and develops heuristics (AHR, staircase/blocks visualization) to reduce shuttling, while proving NP-hardness for the general re-indexing problem and providing a workaround using ancilla blanking. A key theoretical result shows that column-regular qLDPC codes can be compiled with a minimal number of shuttles equal to the code’s column weight $w_c$ under Shor-style syndrome extraction, with empirical results across a broad code family supporting strong shuttle reductions for both Shor and naïve circuits. The paper also demonstrates that irregular LDPC codes can sometimes achieve optimal schedules, and discusses practical implementation aspects like cat-state preparation and ancilla array management. Overall, the work provides a concrete, hardware-aware framework for tailoring quantum error-correcting codes to two-row quantum-dot hardware, with open-source tooling to enable broader exploration and adoption.

Abstract

The ability to physically move qubits within a register allows the design of hardware-specific error-correction codes, which can achieve fault-tolerance while respecting other constraints. In particular, recent advancements have demonstrated the shuttling of electron and hole spin qubits through a quantum dot array with high fidelity. It is therefore timely to explore error correction architectures consisting merely of two parallel quantum dot arrays, an experimentally validated architecture compatible with classical wiring and control constraints. Upon such an architecture, we develop a suite of heuristic methods for compiling any Calderbank-Shor-Steane (CSS) error-correcting code's syndrome-extraction circuit to run with a reduced number of shuttling operations. We demonstrate how column-regular qLDPC codes can be compiled in a provably minimal number of shuttles that is exactly equal to the column weight of the code when Shor-style syndrome extraction is used. We provide tables stating the number of required shuttles for many contemporary codes of interest. In addition, we provide a proof of the NP hardness of minimizing the number of shuttle operations for general codes, even when using Shor syndrome extraction. We also discuss how one could get around this by placing blanks in the ancilla array to achieve minimal shuttles with Shor syndrome extraction on any CSS code, at the cost of longer ancilla arrays

Figures (15)

• Figure 1: Schematic of the quantum dot array hardware. On the left is a possible configuration of this quantum memory, which we parameterize as $\delta^{\tau}=5$, where $\delta^\tau$ represents the offset between the indices of the two rows of qubits (data and ancillary qubits in the case of quantum error correction) at time $\tau$. This $\delta^\tau=5$ implies that cross-array interaction is only permitted between qubit pairs (1,6), (2,7), and (3,8). If we shuttle the bottom row to the left, we would then have the right figure which has $\delta^{\tau+1}=6$ and interaction permitted only between (1,7) and (2,8).
• Figure 2: Example of how qubit re-indexing reduces shuttles. On the left is an unoptimized circuit. $\mathcal{G}$ corresponds to the values of $\delta$ for each gate in the circuit, $\delta(A), \delta(B),$ and $\delta(C)$. $|\mathcal{G}|_0$ denotes the number of unique elements in $\mathcal{G}$. Notice that to run this circuit on a $2 \times n$ architecture, two shuttles (or $|\mathcal{G}|_0$ positions) are necessary. On the right is the same circuit, except the indexing of the qubits has changed, which then allows the same circuit as before to run, this time only requiring a single shuttle.
• Figure 3: Measuring the parity of $Z_1Z_2Z_3Z_4$ via two types of syndrome extraction. a) Naive syndrome extraction: Parity measurement is given by coupling all pertinent data qubits to single ancillary qubit, and then performing a measurement. b) Shor-style syndrome extraction shor1997faulttolerant: Each data qubit indicated by a non-identity element in a weight $w$ stabilizer is coupled to its own ancillary qubit. For that single parity check, the participating ancilla are beforehand prepared in a $w$-qubit GHZ state. Each ancilla is then measured, and the classical XOR is taken over the resulting values to yield a the parity of the stabilizer measurement. Double lines here represent the flow of classical information.
• Figure 4: Illustration of primitive sets under different re-orderings. On the left is an arbitrary circuit, and below are the $\delta$ values for each of its gates, $\mathcal{G}$, as well as the number of unique values, $|\mathcal{G}|_0$. Below that, we partition $\mathcal{G}$ into three sets, each corresponding to the gates connected to each ancillary qubit. Below each set is a "primitive set" with some integer being added element-wise. This addition encodes the current indexing of the ancillary qubits. On the right, is a different way of indexing these ancillary qubits. Notice that although the values in $\mathcal{G}$ have changed, the primitive sets remain the same.
• Figure 5: Visualization of block placement. a) Primitive sets of the circuit in Fig. \ref{['fig:reindexing_example2']} represented in our so-called "block form". The green blocks represent the absence of an element in the set, while the blue blocks represent the presence of the corresponding element. Placing these blocks on the staircase represent assignments. For examples, placing $P_6$ on +1 would cause all its blocks to shift to the right by one. After placing all blocks, all columns that contain at least one blue block would correspond to a unique element in $\mathcal{G}$, and recall unique values in $\mathcal{G}$ correspond to different configurations of the $2 \times n$ architecture and therefore require shuttles. b) Optimal placement for this problem.

Theorems & Definitions (8)

• Lemma 1
• proof
• Lemma 2
• proof
• Lemma 3
• proof
• Lemma 4
• proof