Neuromorphic Retina: An FPGA-based Emulator
Prince Philip, Pallab Kumar Nath, Kapil Jainwal, Andre van Schaik, Chetan Singh Thakur
TL;DR
The paper tackles the challenge of creating a biologically plausible retinal model suitable for prosthetics by implementing a neuromorphic digital retina on an FPGA. It introduces a Convis-inspired architecture with a center-surround outer plexiform layer (OPL) using non-separable spatio-temporal filters, luminance adaptation via a high-pass photoreceptor stage, a bipolar-level contrast gain control, and an inner plexiform layer (IPL) with leaky integrate-and-fire (LIF) ganglion cells that generate spikes. The OPL computes $I_OPL = λ_OPL (C - ω_OPL S)$ with $C = G_C * T_{w,τ} * E_{τC} * L$ and $S = G_S * E_{τS} * C$. The bipolar gain control is described by $C dV_{Bip}/dt = I_{OPL} - g_A V_{Bip}$ and $g_A = G_A * E_A * Q(V_{Bip})$, with $Q(V_{Bip}) = g^0_A + λ_A V_{Bip}^2$, enabling adaptive luminance/contrast processing and tunable phasic/tonic responses; the implementation supports 128×128 input at 200fps on an Artix-7 and demonstrates real-time operation for retinal prosthesis applications.
Abstract
Implementing accurate models of the retina is a challenging task, particularly in the context of creating visual prosthetics and devices. Notwithstanding the presence of diverse artificial renditions of the retina, the imperative task persists to pursue a more realistic model. In this work, we are emulating a neuromorphic retina model on an FPGA. The key feature of this model is its powerful adaptation to luminance and contrast, which allows it to accurately emulate the sensitivity of the biological retina to changes in light levels. Phasic and tonic cells are realizable in the retina in the simplest way possible. Our FPGA implementation of the proposed biologically inspired digital retina, incorporating a receptive field with a center-surround structure, is reconfigurable and can support 128*128 pixel images at a frame rate of 200fps. It consumes 1720 slices, approximately 3.7k Look-Up Tables (LUTs), and Flip-Flops (FFs) on the FPGA. This implementation provides a high-performance, low-power, and small-area solution and could be a significant step forward in the development of biologically plausible retinal prostheses with enhanced information processing capabilities
