Modular Compilation for Quantum Chiplet Architectures

TL;DR

This work tackles the challenge of compiling quantum programs for modular, chiplet-based quantum processors where inter-module links are non-universal and heterogeneous. It introduces SEQC, a Stratify-Elaborate Quantum Compiler with a module-aware peephole correction pass, enabling hierarchical, parallelized compilation that minimizes inter-module gates and respects module connectivity. The approach yields up to $9.3\%$ average fidelity gains (peaking at $49.99\%$) and accelerates compilation by up to $3.27\times$ on average (up to $6.74\times$) compared with a module-agnostic baseline, with even larger benefits at scale. These results demonstrate SEQC’s potential to scale quantum compilation for future large-scale, hybrid modular quantum systems while maintaining or improving execution fidelity and run-time performance for practical workloads.

Abstract

As quantum computing technology matures, industry is adopting modular quantum architectures to keep quantum scaling on the projected path and meet performance targets. However, the complexity of chiplet-based quantum devices, coupled with their growing size, presents an imminent scalability challenge for quantum compilation. Contemporary compilation methods are not well-suited to chiplet architectures - in particular, existing qubit allocation methods are often unable to contend with inter-chiplet links, which don't necessarily support a universal basis gate set. Furthermore, existing methods of logical-to-physical qubit placement, swap insertion (routing), unitary synthesis, and/or optimization, are typically not designed for qubit links of significantly varying latency or fidelity. In this work, we propose SEQC, a hierarchical parallelized compilation pipeline optimized for chiplet-based quantum systems, including several novel methods for qubit placement, qubit routing, and circuit optimization. SEQC attains a $9.3\%$ average increase in circuit fidelity (up to $49.99\%$). Additionally, owing to its ability to parallelize compilation, SEQC achieves $3.27\times$ faster compilation on average (up to $6.74\times$) over a chiplet-unaware Qiskit baseline.

Figures (12)

• Figure 1: Peephole correction for inter-module gates that are unimplementable on hardware (i.e., non-SWAP, shown in red).
• Figure 2: High-level diagram of SEQC. Elements in red reflect modifications from existing compiler designs.
• Figure 3: Step-by-step example of inter-module compilation in the Stratification stage.
• Figure 4: Step-by-step example of intra-module compilation in the Elaboration stage. Gates that cannot be implemented on hardware are shown in red.
• Figure 5: Examples of benchmark applications for 5-qubit circuits.