Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding

TL;DR

The paper tackles efficient SNN deployment by addressing spike-encoding and hardware processing. It combines end-to-end learning of spike encoding with a differential-time SNN accelerator that uses a Spike Sorter, Neuron Cores, LOPD, and Layer Controller, and it incorporates the LIF update $P_k = P_{k-1} \beta^{\Delta t} + \sum_i w_i s_i - s_{out}$ with $\theta=1$, $\beta=0.5$. It demonstrates that a lif-only network using patch-based encoding can reach >99% MNIST accuracy on medium-FPGA hardware with no multiplications and sub-300 μs latency. This work offers a practical path toward energy-efficient, high-accuracy SNN accelerators by integrating learnable encoding with differential-time spike processing.

Abstract

Spiking Neural Networks (SNNs) have garnered attention over recent years due to their increased energy efficiency and advantages in terms of operational complexity compared to traditional Artificial Neural Networks (ANNs). Two important questions when implementing SNNs are how to best encode existing data into spike trains and how to efficiently process these spike trains in hardware. This paper addresses both of these problems by incorporating the encoding into the learning process, thus allowing the network to learn the spike encoding alongside the weights. Furthermore, this paper proposes a hardware architecture based on a recently introduced differential-time representation for spike trains allowing decoupling of spike time and processing time. Together these contributions lead to a feedforward SNN using only Leaky-Integrate and Fire (LIF) neurons that surpasses 99% accuracy on the MNIST dataset while still being implementable on medium-sized FPGAs with inference times of less than 295us.

Figures (5)

• Figure 1: Hardware architecture of network with multiple neuron layers. Data signals are colored black, while control signals are colored blue.
• Figure 2: Spike Sorter design with 4 inputs.
• Figure 3: Neuron Core requiring only one register, one comparator, a multiplexer and one adder.
• Figure 4: Patch-wise selection of the pixels with subsequent neuron activation with weights learned for encoding.
• Figure 5: Results of network evaluation on MNIST dataset with patch sizes ranging from 5x5 to 9x9, averaged over 96 runs respectively. Arbitrary weights (A) are quantized to $w=2^i$ (V1) and $w\in\{-1,0,1\}$ (V2).