Solving Boolean satisfiability problems with resistive content addressable memories
Giacomo Pedretti, Fabian Böhm, Tinish Bhattacharya, Arne Heittman, Xiangyi Zhang, Mohammad Hizzani, George Hutchinson, Dongseok Kwon, John Moon, Elisabetta Valiante, Ignacio Rozada, Catherine E. Graves, Jim Ignowski, Masoud Mohseni, John Paul Strachan, Dmitri Strukov, Ray Beausoleil, Thomas Van Vaerenbergh
TL;DR
The paper addresses the challenge of solving high-order SAT problems efficiently on hardware by introducing KLIMA, a k-local in-memory accelerator that combines resistive CAMs (TCAM) with Dot-Product Engines (DPEs) to map CNF-SAT natively without auxiliary variables. This hardware-software co-design enables parallel computation of make, break, and gain metrics to drive stochastic local search heuristics, achieving up to $182\times$ energy-to-solution improvements over digital baselines and compelling performance versus CPU WalkSAT. By leveraging in-memory computing and a native CNF representation, KLIMA reduces coupling term overhead and enables flexible exploration of solvers such as GNSAT, MNSAT, and WalkSAT variants. The results suggest KLIMA as a scalable building block for optimization and sampling workloads in heterogeneous systems, with substantial practical impact for industry-scale SAT and related optimization tasks.
Abstract
Solving optimization problems is a highly demanding workload requiring high-performance computing systems. Optimization solvers are usually difficult to parallelize in conventional digital architectures, particularly when stochastic decisions are involved. Recently, analog computing architectures for accelerating stochastic optimization solvers have been presented, but they were limited to academic problems in quadratic polynomial format. Here we present KLIMA, a k-Local In-Memory Accelerator with resistive Content Addressable Memories (CAMs) and Dot-Product Engines (DPEs) to accelerate the solution of high-order industry-relevant optimization problems, in particular Boolean Satisfiability. By co-designing the optimization heuristics and circuit architecture we improve the speed and energy to solution up to 182x compared to the digital state of the art.
