LUCAS: A Low-Power Ultra-Low Jitter Compact ASIC for SiPM Targetting ToF-CT
Seyed Arash Katourani
TL;DR
The paper addresses the need for fast, low-jitter SiPM readout in ToF-CT with high channel counts. It introduces LUCAS, an 8-channel analog front-end implemented in 65 nm LP CMOS at 1.2 V, featuring a low-input-impedance preamplifier based on a flipped voltage follower and a comparator, augmented by a bypass path and dual-bias scheme to optimize gain and jitter performance. Simulation results predict per-channel power around 3.2 mW, timing jitter below 40 ps FWHM SPTR, and a 3.9 GHz unity-gain bandwidth, with detailed SiPM modeling and wire-bonding effects included; the device was submitted for fabrication with August 2023 delivery. The work enables compact, high-density timing readouts suitable for ToF-CT and related imaging modalities, with planned future expansions to 64/96 channels and integration of TDCs and specialized SiPM assemblies to further reduce parasitics and heat.
Abstract
We present LUCAS (Low power Ultra-low jitter Compact ASIC for SiPM), an analog front-end for Silicon Photomultipliers (SiPM) targeting fast timing detectors in Time-of-Flight Computed Tomography (ToF-CT). LUCAS features a very low input impedance preamplifier followed by a voltage comparator. It is designed in TSMC 65 nm low-power CMOS technology with a power supply of 1.2 V. Our first 8-channel prototype has been sent to fabrication and will be received in August 2023. Post-layout simulations predict less than 40 ps FWHM SPTR jitter and an approximate power consumption of 3.2 mW per channel. The front end is suitable for applications with rigorous jitter requirements and high event rates, thanks to its 3.9 GHz unity-gain bandwidth. The front-end compact form factor will facilitate its incorporation into systems demanding high channel densities.
