QSteed: A Resource-Virtualized and Hardware-Aware Quantum Compilation Framework for Real Quantum Computing Processors

TL;DR

QSteed addresses the challenge of compiling quantum programs for real hardware by introducing a resource-virtualization framework that abstracts heterogeneous backends into a queryable VQPU database. Its select-then-compile workflow first locates an optimal VQPU based on circuit structure and fidelity, then performs hardware-aware transpilation within a targeted subregion, reducing compilation time while maintaining or enhancing circuit fidelity. The core contributions are a four-layer abstraction (QPU, StdQPU, SubQPU, VQPU), SubQPU discovery heuristics, fidelity- and structure-guided VQPU selection, and a modular DAG-based transpiler with noise-aware routing, validated on Quafu Baihua and Willow data. Experimental results show QSteed often outperforms Qiskit and Pytket in compilation speed with comparable or higher fidelity, indicating practical impact for quantum cloud platforms in the NISQ era and potential extension to diverse hardware backends.

Abstract

As quantum computing systems continue to scale up and become more clustered, efficiently compiling user quantum programs into high fidelity executable sequences on real hardware remains a key challenge for current quantum compilation systems. In this study, we introduce a system software framework that integrates resource virtualization and hardware aware compilation for real quantum computing processors, termed QSteed. QSteed virtualizes quantum processors through a four layer abstraction hierarchy comprising the Real Quantum Processing Unit (QPU), Standard QPU (StdQPU), Substructure of the QPU (SubQPU), and Virtual QPU (VQPU). These abstractions, together with calibration data, device topology, and noise descriptors, are maintained in a dedicated database to enable unified and fine grained management across superconducting quantum platforms. At run time, the modular compiler queries the database to match each incoming circuit with the most suitable VQPU, after which it confines layout, routing, gate resynthesis, and noise adaptive optimizations to that virtual subregion. The complete stack has been deployed on the Quafu superconducting cluster, where experimental runs confirm the correctness of the virtualization model and the efficacy of the compiler without requiring modifications to user code. By integrating resource virtualization with a select-then-compile workflow, QSteed demonstrates a robust architecture for compiling programs on noisy superconducting processors. This architectural approach offers a promising path towards efficient compilation needs across various superconducting quantum computing platforms in the noisy intermediate scale quantum (NISQ) era.

Figures (18)

• Figure 1: QSteed system architecture. It consists primarily of two components: the quantum compiler and the quantum computing resource manager. The manager models the quantum chip at various abstraction levels, including QPU, StdQPU, SubQPU, and VQPU. These representations are stored in a quantum computing resource virtualization database, enabling unified management of quantum backend devices. The compiler queries the virtualization database to compile the user task onto the optimal physical qubits, returning the optimized executable QASM circuit along with relevant compilation information.
• Figure 2: (a) The schematic of the Baihua quantum chip, with blue regions representing 122 connected qubits. (b) The 6-qubit VQPU structure within the Baihua quantum chip, where the red box highlights the target VQPU (the mapping from virtual qubits $v$ to physical qubits $q$ is $v_{\{0,1,2,3,4,5\}} \to q_{\{61,62,63,74,75,76\}}$) with the structure most similar to the circuit in (c). (c) Quantum circuit. (d) Weighted graph representation of the quantum circuit, where the nodes represent qubits, the edges represent two-qubit gates, and the edge weights represent the number of two-qubit gates.
• Figure 3: The quantum circuit transpilation and optimization workflow adopts a modular design, consisting of core components: Transpiler, Pass, PassFlow, Model, and Backend. The target VQPU is first modeled as a Backend object and then abstracted into a Model object. During the transpilation process, the Model object stores and passes the parameter data required for transpilation. The transpiler selects a predefined or user-defined PassFlow based on the optimization level to execute the transpilation process. A PassFlow is composed of a sequence of functional components, each responsible for a specific transpilation task. The transpilation process is primarily performed on the directed acyclic graph (DAG) representation of the quantum circuit. Upon completion, the transpiled quantum circuit is output.
• Figure 4: Benchmarking results of the Baihua quantum chip. (a) Single-qubit process infidelities from CSB. (b) CNOT gate error rates from CSB. (c) CNOT gate error rates from XEB. NA means the error rate is too high or gates are unavailable.
• Figure 5: Performance comparison of different quantum compilers on the Baihua quantum processor. The results for each benchmark circuit represent the median of 5 runs, while the results for random types are averaged over more than 50 runs of randomly generated circuits. Error bars indicate the standard error of the mean. The vertical axes, from top to bottom, represent the compiled circuit depth, the number of CNOT gates, the transpilation time, and the Hellinger fidelity $F_H$ (higher is better). Except for the random circuits, the circuit names (trailing number denotes qubits) on the horizontal axis are derived from the QASMBench benchmarking suite 10.1145/3550488.