TransPlace: Transferable Circuit Global Placement via Graph Neural Network

TL;DR

TransPlace tackles global placement for circuits with millions of mixed-size cells by learning transferable placement knowledge through a graph-based Netlist Graph and a two-stage inductive-plus-fine-tuning pipeline. It introduces Cell-flow for relative positioning, SE(2)-invariant encoding/decoding to preserve geometry, and the Transferable Placement Graph Neural Network (TPGNN) to perform topology- and geometry-aware message passing, followed by circuit-adaptive fine-tuning to adapt to unseen designs. Across multiple benchmarks, TransPlace achieves a 1.2× speedup, reduces congestion by ~30%, and yields improvements in timing (~9%) and wirelength (~5%), while demonstrating strong cross-design transfer and cross-objective robustness. The approach offers a scalable, learning-based alternative to traditional placers, providing warm starts and potential acceleration for practical chip-design workflows.

Abstract

Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%.

Figures (5)

• Figure 1: A schematic illustration of TransPlace. TransPlace contains two stages: Inductive Placement and Circuit-adaptive Fine-tuning. (a) Inductive Placement efficiently generates relative cell positions in one shot. It constructs the Cell-flow and Netlist Graph, applies message-passing on the two graphs to obtain cell and net representations, fuses and updates the hidden representations, and reads out relative position $\rho, \Delta\theta$. (b) Circuit-adaptive Fine-tuning decodes the relative positions within cell-flow into absolute positions and performs iterative gradient-based optimization.
• Figure 2: Overview of Netlist Graph, Cell-flow, cell-path, $f_{\rm INCOME}$, and $f_{\rm PATH}$.
• Figure 3: Visualizations of comparisons on superblue5. (a) Congestion visualization of the placement generated by DREAMPlace and TransPlace. The grey parts denote the cells, and the red dots indicate that there is congestion. Density of red dots indicates the level of congestion. (b) Overall comparison of vertical and horizontal overflow (lower overflow implies better performance). (c) Distribution of timing path slack for placements. A higher proportion of smaller slack indicates better performance.
• Figure 4: Extracting sub-netlist graphs and coarsening original netlist graph.
• Figure 5: The algorithm of constructing cell-flow from a netlist graph.

Theorems & Definitions (2)

• definition 1: Netlist Graph
• definition 2: Cell-flow