Distributed and heterogeneous tensor-vector contraction algorithms for high performance computing

TL;DR

This work delivers distributed-memory, mode-oblivious TVC and a highly optimized distributed HOPM variant (dHOPM3) for dense tensors. It shows that dTVC and dHOPM3 can approach a significant fraction of memory bandwidth across CPU, GPU, and high-bandwidth memory architectures, while reducing streamed memory through a three-buffer strategy and supporting mixed-precision execution. The study provides analytical guidance on tensor splitting, develops task-based parallelism to improve overlap and efficiency, and demonstrates competitive performance against state-of-the-art tensor libraries, with notable memory savings for higher-order tensors. The findings pave the way for scalable, dense multilinear algebra on heterogeneous HPC systems and suggest directions for CUDA-native implementations and deeper integration into tensor frameworks.

Abstract

The tensor-vector contraction (TVC) is the most memory-bound operation of its class and a core component of the higher-order power method (HOPM). This paper brings distributed-memory parallelization to a native TVC algorithm for dense tensors that overall remains oblivious to contraction mode, tensor splitting and tensor order. Similarly, we propose a novel distributed HOPM, namely dHOPM3, that can save up to one order of magnitude of streamed memory and is about twice as costly in terms of data movement as a distributed TVC operation (dTVC) when using task-based parallelization. The numerical experiments carried out in this work on three different architectures featuring multi-core and accelerators confirm that the performances of dTVC and dHOPM3 remain relatively close to the peak system memory bandwidth (50%-80%, depending on the architecture) and on par with STREAM benchmark figures. On strong scalability scenarios, our native multi-core implementations of these two algorithms can achieve similar and sometimes even greater performance figures than those based upon state-of-the-art CUDA batched kernels. Finally, we demonstrate that both computation and communication can benefit from mixed precision arithmetic also in cases where the hardware does not support low precision data types natively.

Figures (7)

• Figure 1: One-dimensional optimal splittings ($s=0,1,2$) using up to three processes ($p=3$) for a third-order tensor $\mathcal{A}^{2 \times 3 \times 4}$ stored in last-order, nonhierarchical memory layout.
• Figure 2: (a) memory ratio ($\eta^{-1}$) incurred by the classical, dHOPM implementation and (b) memory ratio ($H^{-1}$) between this canonical version and dHOPM$_3$ as a function of the nondimensional number of processes ($\hat{p}$) and the nondimensional splitting dimension ($\hat{s}$). Results correspond to the third- and tenth-order tensors of Table \ref{['tab:tensors']}.
• Figure 3: Paraver traces from the hybrid execution of (a) the dHOPM$_3$ algorithm and (b) a zoom-in view of the last $k$ internal contractions of iteration $j=0$ using the tenth-order tensor of Table \ref{['tab:tensors']} split along its last dimension. Traces obtained on MN4 using 4 MPI processes, 8 cores per process, and 32 OmpSs-2 tasks per process for illustration purposes.
• Figure 4: dTVC normalized throughput (including global assembly of the output tensor) measured as the number of iterations per second per MPI process (it/sp) over all contraction modes and all splitting dimensions for the tensors of Table \ref{['tab:tensors']}. Strong scalability results using up to 8 MPI processes on MN4 employing our proposed distributed TVC algorithm (solid fill) and the CTF implementation (pattern fill).
• Figure 5: dTVC normalized, averaged bandwidth and averaged throughput over all contraction modes and all splitting dimensions for the tensors of Table \ref{['tab:tensors']}. Strong scalability results using up to 128 MPI processes on (a)--(b) MN4, (c)--(d) CTE-ARM, and (e)--(f) CTE-POWER.