Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Integrated AHB to APB Bridge Using Raspberry Pi and Artix-7 FPGA

Gopi Chand Ananthu, Riadul Islam

TL;DR

This work addresses the challenge of integrating high-speed AHB components with low-power APB peripherals in System-on-Chip designs by implementing an AHB-to-APB bridge on an Artix-7 FPGA, with a Raspberry Pi acting as the SPI master. The methodology employs a five-module architecture (Raspberry Pi, SPI Slave, Mapper1, Bridge Top, Mapper2) and a three-block Bridge Top consisting of an AHB Slave Interface, an APB FSM Controller, and an APB Interface to translate protocols and synchronize across clock domains. The approach is validated through Verilog-based simulations and FPGA synthesis using Vivado, Synopsys DC, and ICC2, with testbenches and SPI data management implemented in Python. Results demonstrate correct protocol translation, proper data-path mappings, and reliable bidirectional communication between AHB masters and APB peripherals, supported by detailed area, power, and timing analyses that confirm feasibility for practical SoC deployments.

Abstract

This project focuses on the design and implementation of an AHB to APB Bridge for efficient communication in System-on-Chip (SoC) architectures. The Advanced High-performance Bus (AHB) is used for high-speed operations, typically connecting processors and memory, while the Advanced Peripheral Bus (APB) is optimized for low-power, low-speed peripheral devices. The AHB to APB Bridge serves as an interface that converts complex, high-speed AHB transactions into simpler, single-cycle APB transactions, enabling seamless data transfer between fast components and slower peripherals. The bridge manages clock domain synchronization, transaction conversion, and flow control, ensuring compatibility between AHB's burst transfers and APB's non-pipelined protocol. Implemented in Verilog and simulated on FPGA using Xilinx Vivado, this bridge design provides a robust solution for integrating high-performance and low-power components within a single SoC. This project also evaluates the bridge's functionality and performance through testbenches covering various operational scenarios, validating its efficiency in handling diverse system requirements.

Integrated AHB to APB Bridge Using Raspberry Pi and Artix-7 FPGA

TL;DR

This work addresses the challenge of integrating high-speed AHB components with low-power APB peripherals in System-on-Chip designs by implementing an AHB-to-APB bridge on an Artix-7 FPGA, with a Raspberry Pi acting as the SPI master. The methodology employs a five-module architecture (Raspberry Pi, SPI Slave, Mapper1, Bridge Top, Mapper2) and a three-block Bridge Top consisting of an AHB Slave Interface, an APB FSM Controller, and an APB Interface to translate protocols and synchronize across clock domains. The approach is validated through Verilog-based simulations and FPGA synthesis using Vivado, Synopsys DC, and ICC2, with testbenches and SPI data management implemented in Python. Results demonstrate correct protocol translation, proper data-path mappings, and reliable bidirectional communication between AHB masters and APB peripherals, supported by detailed area, power, and timing analyses that confirm feasibility for practical SoC deployments.

Abstract

This project focuses on the design and implementation of an AHB to APB Bridge for efficient communication in System-on-Chip (SoC) architectures. The Advanced High-performance Bus (AHB) is used for high-speed operations, typically connecting processors and memory, while the Advanced Peripheral Bus (APB) is optimized for low-power, low-speed peripheral devices. The AHB to APB Bridge serves as an interface that converts complex, high-speed AHB transactions into simpler, single-cycle APB transactions, enabling seamless data transfer between fast components and slower peripherals. The bridge manages clock domain synchronization, transaction conversion, and flow control, ensuring compatibility between AHB's burst transfers and APB's non-pipelined protocol. Implemented in Verilog and simulated on FPGA using Xilinx Vivado, this bridge design provides a robust solution for integrating high-performance and low-power components within a single SoC. This project also evaluates the bridge's functionality and performance through testbenches covering various operational scenarios, validating its efficiency in handling diverse system requirements.
Paper Structure (27 sections, 6 figures, 4 tables)

This paper contains 27 sections, 6 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Motivation
  3. Contributions
  4. Background
  5. Proposed Methodology
  6. System Architecture and Module Breakdown
  7. Raspberry Pi
  8. SPI slave
  9. Mapper1
  10. Bridge Top
  11. Mapper2
  12. AHB to APB Bridge Architecture
  13. AHB Slave Interface
  14. APB FSM Controller
  15. APB Interface
  16. ...and 12 more sections

Figures (6)

  • Figure 1: Integrated AHB to APB Bridge using the Raspberry pi and Artix-7.
  • Figure 2: AHB to APB Bridge.
  • Figure 3: Finite State Machine.
  • Figure 4: Simulation result for APB FSM Controller shows the output signals Pwrite,Penable high after the Hwrite and Valid goes high.
  • Figure 5: Simulation result for AHB to APB.
  • ...and 1 more figures