TReCiM: Lower Power and Temperature-Resilient Multibit 2FeFET-1T Compute-in-Memory Design

TL;DR

This work tackles the temperature-induced accuracy degradation of subthreshold FeFET-based compute-in-memory by introducing TReCiM, a temperature-resilient multibit 2FeFET-1T CiM design. The core contributions are a two-FET clamp cell with a CTAT feedback mechanism that stabilizes MAC operations across 0–85°C, and an 8-row CiM array with a 3-bit flash ADC for efficient analog-to-digital conversion. System-level validation via NeuroSim on VGG-8 with CIFAR-10 shows 91.31% inference accuracy for 2-bit storage and 92.00% for binary storage, along with 48.03 TOPS/W energy efficiency at a 128×128 array. The results demonstrate robust temperature resilience and high energy efficiency, enabling reliable edge AI inference with FeFET CiM at scale.

Abstract

Compute-in-memory (CiM) emerges as a promising solution to solve hardware challenges in artificial intelligence (AI) and the Internet of Things (IoT), particularly addressing the "memory wall" issue. By utilizing nonvolatile memory (NVM) devices in a crossbar structure, CiM efficiently accelerates multiply-accumulate (MAC) computations, the crucial operations in neural networks and other AI models. Among various NVM devices, Ferroelectric FET (FeFET) is particularly appealing for ultra-low-power CiM arrays due to its CMOS compatibility, voltage-driven write/read mechanisms and high ION/IOFF ratio. Moreover, subthreshold-operated FeFETs, which operate at scaling voltages in the subthreshold region, can further minimize the power consumption of CiM array. However, subthreshold-FeFETs are susceptible to temperature drift, resulting in computation accuracy degradation. Existing solutions exhibit weak temperature resilience at larger array size and only support 1-bit. In this paper, we propose TReCiM, an ultra-low-power temperature-resilient multibit 2FeFET-1T CiM design that reliably performs MAC operations in the subthreshold-FeFET region with temperature ranging from 0 to 85 degrees Celcius at scale. We benchmark our design using NeuroSim framework in the context of VGG-8 neural network architecture running the CIFAR-10 dataset. Benchmarking results suggest that when considering temperature drift impact, our proposed TReCiM array achieves 91.31% accuracy, with 1.86% accuracy improvement compared to existing 1-bit 2T-1FeFET CiM array. Furthermore, our proposed design achieves 48.03 TOPS/W energy efficiency at system level, comparable to existing designs with smaller technology feature sizes.

Figures (9)

• Figure 1: (a) FeFET structure and binary states. By applying different write voltages, the FeFET can be programmed to different polarization directions, resulting in two distinct states. (b) Characteristic of binary states (low-V$_{TH}$/high-V$_{TH}$) at different temperatures. The variation under operating temperature causes non-negligible output swings. (c) Simulated MLC characteristics with more than 3-bit V$_{TH}$ states based on Preisach FeFET model.
• Figure 2: Schematic of the proposed 2FeFET-1T cell design for TReCiM array. The cell shown here can store 2-bit data. During the write stages, the stored data is written by voltages on WLs. During the read stages, the 2FeFET-1T cell performs MAC operations with different stored data and inputs.
• Figure 3: The feedback loop for temperature drift compensation. The output current drop will also rise back as the temperature decreases.
• Figure 4: Simulated I$_{SL}$-V$_{read}$ characteristics of the 2FeFET-1T cell with varying states stored in the cell. The cells with different stored states show linearly growing current output at given operating voltage.
• Figure 5: Macro organization of 2FeFET-1T CiM system. The CiM system consists of CiM array, ADC and peripheral circuits (MUX, adder, etc.).