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Aligning Netlist to Source Code using SynAlign

Sakshi Garg, Jose Renau

TL;DR

SynAlign tackles the challenge of losing source-code correlation after synthesis by automatically aligning post-optimized netlists to the original HDL source using a multi-level graph-alignment framework. It introduces Anchor Points and a sequence of matching stages—Full+Half, Partial, and Surrounding—to achieve robust, many-to-many mappings without modifying compiler or synthesis tools. Empirical evaluations across open-source and industrial flows show strong tolerance to netlist noise (up to about $60\%$) and fast runtime (often under $20$ seconds) with substantial accuracy, including $75\%$ averaged across benchmarks. The work promises improved back-annotation, faster design iterations, and broader applicability to HDLs convertible to Verilog with LoC information, potentially reducing time-to-market in chip design.

Abstract

In current chip design processes, using multiple tools to obtain a gate-level netlist often results in the loss of source code correlation. SynAlign addresses this challenge by automating the alignment process, simplifying iterative design, reducing overhead, and maintaining correlation across various tools. This enhances the efficiency and effectiveness of chip design workflows. Improving characteristics such as frequency through iterative design is essential for enhancing accelerators and chip designs. While synthesis tools produce netlists with critical path information, designers often lack the tools to trace these netlist cells back to their original source code. Mapping netlist components to source code provides early feedback on timing and power for frontend designers. SynAlign automatically aligns post-optimized netlists with the original source code without altering compilers or synthesis processes. Its alignment strategy relies on the consistent design structure throughout the chip design cycle, even with changes in compiler flow. This consistency allows engineers to maintain a correlation between modified designs and the original source code across various tools. Remarkably, SynAlign can tolerate up to 61\% design net changes without impacting alignment accuracy.

Aligning Netlist to Source Code using SynAlign

TL;DR

SynAlign tackles the challenge of losing source-code correlation after synthesis by automatically aligning post-optimized netlists to the original HDL source using a multi-level graph-alignment framework. It introduces Anchor Points and a sequence of matching stages—Full+Half, Partial, and Surrounding—to achieve robust, many-to-many mappings without modifying compiler or synthesis tools. Empirical evaluations across open-source and industrial flows show strong tolerance to netlist noise (up to about ) and fast runtime (often under seconds) with substantial accuracy, including averaged across benchmarks. The work promises improved back-annotation, faster design iterations, and broader applicability to HDLs convertible to Verilog with LoC information, potentially reducing time-to-market in chip design.

Abstract

In current chip design processes, using multiple tools to obtain a gate-level netlist often results in the loss of source code correlation. SynAlign addresses this challenge by automating the alignment process, simplifying iterative design, reducing overhead, and maintaining correlation across various tools. This enhances the efficiency and effectiveness of chip design workflows. Improving characteristics such as frequency through iterative design is essential for enhancing accelerators and chip designs. While synthesis tools produce netlists with critical path information, designers often lack the tools to trace these netlist cells back to their original source code. Mapping netlist components to source code provides early feedback on timing and power for frontend designers. SynAlign automatically aligns post-optimized netlists with the original source code without altering compilers or synthesis processes. Its alignment strategy relies on the consistent design structure throughout the chip design cycle, even with changes in compiler flow. This consistency allows engineers to maintain a correlation between modified designs and the original source code across various tools. Remarkably, SynAlign can tolerate up to 61\% design net changes without impacting alignment accuracy.
Paper Structure (19 sections, 12 figures, 2 tables)

This paper contains 19 sections, 12 figures, 2 tables.

Table of Contents

  1. Introduction
  2. SynAlign Algorithm
  3. Anchor Points Matching
  4. Full+Half Matching
  5. Partial Matching
  6. Surrounding Matching
  7. Evaluation and Discussion
  8. Netlist to Netlist (NL2NL) Evaluation
  9. Manual Accuracy Evaluation
  10. Performace evaluation
  11. Insights to evaluation
  12. The first walkthrough of alignment analyzed as inaccurate.
  13. The second walkthrough of alignment analyzed as inaccurate.
  14. A walkthrough of alignment analyzed as accurate.
  15. Limitations and Future Work
  16. ...and 4 more sections

Figures (12)

  • Figure 1: SynAlign Vs. current industrial practice.
  • Figure 2: (a) Source code example with aligned part highlighted. (b) Reference graph ($G_{ref}$). (c) synthesized graph ($G_{synth}$) with annotations.
  • Figure 3: Concept demonstration of Surrounding Matching with collapsing nodes.
  • Figure 4: Surrounding Matching depicting the surrounding cells with same LoC used to resolve the source location of node "op".
  • Figure 5: NL2NL accuracy Plot for different RocketTile compilations
  • ...and 7 more figures