Table of Contents
Fetching ...

12-bit Delta-Sigma ADC operating at a temperature of up to 250C in Standard 0.18 $μ$m SOI CMOS

Christian Sbrana, Alessandro Catania, Tommaso Toschi, Sebastiano Strangio, Giuseppe Iannaccone

TL;DR

This work tackles the challenge of reliable high-temperature analog-to-digital conversion by demonstrating a second-order discrete-time delta-sigma ADC implemented in automotive-grade SOI CMOS (0.18 μm, XFAB XT018) capable of operation up to $250^{\circ}$C, well beyond the process qualification of $-40^{\circ}$C to $175^{\circ}$C. It introduces temperature-aware design techniques, including dummy-transistor leakage compensation, clock boosting for pass-gates, and electromigration-aware layout, to stabilize leakage and maintain accuracy. The device achieves a 12-bit ENOB with SNR exceeding $93$ dB at $250^{\circ}$C, consumes about $44$ mW, and occupies $0.065~\mathrm{mm^2}$ with a $13.7\%$ area overhead for high-temperature circuitry, yielding a Schreier FoM of 140 dB at the maximum temperature. These results position high-temperature SOI-CMOS Delta-Sigma ADCs as viable components for harsh environments such as gas/oil extraction and aeronautics, and indicate a path toward even higher temperatures with continued design optimization and interconnect/material advances.

Abstract

Some applications require electronic systems to operate at extremely high temperature. Extending the operating temperature range of automotive-grade CMOS processes -- through the use of dedicated design techniques -- can provide an important cost-effective advantage. We present a second-order discrete-time delta-sigma analog-to-digital converter operating at a temperature of up to 250 $^\circ$C, well beyond the 175 $^\circ$C qualification temperature of the automotive-grade CMOS process used for its fabrication (XFAB XT018). The analog-to-digital converter incorporates design techniques that are effective in mitigating the adverse effects of the high temperature, such as increased leakage currents and electromigration. We use configurations of dummy transistors for leakage compensation, clock-boosting methods to limit pass-gate cross-talk, and we optimized the circuit architecture to ensure stability and accuracy at high temperature. Comprehensive measurements demonstrate that the analog-to-digital converter achieves a signal-to-noise ratio exceeding 93 dB at 250 $^\circ$C, with an effective number of bits of 12, and a power consumption of only 44~mW. The die area of the converter is only 0.065~mm$^2$ and the area overhead of the high-temperature mitigation circuits is only 13.7%. The Schreier Figure of Merit is 140~dB at the maximum temperature of 250 $^\circ$C, proving the potential of the circuit for reliable operation in challenging applications such as gas and oil extraction and aeronautics.

12-bit Delta-Sigma ADC operating at a temperature of up to 250C in Standard 0.18 $μ$m SOI CMOS

TL;DR

This work tackles the challenge of reliable high-temperature analog-to-digital conversion by demonstrating a second-order discrete-time delta-sigma ADC implemented in automotive-grade SOI CMOS (0.18 μm, XFAB XT018) capable of operation up to C, well beyond the process qualification of C to C. It introduces temperature-aware design techniques, including dummy-transistor leakage compensation, clock boosting for pass-gates, and electromigration-aware layout, to stabilize leakage and maintain accuracy. The device achieves a 12-bit ENOB with SNR exceeding dB at C, consumes about mW, and occupies with a area overhead for high-temperature circuitry, yielding a Schreier FoM of 140 dB at the maximum temperature. These results position high-temperature SOI-CMOS Delta-Sigma ADCs as viable components for harsh environments such as gas/oil extraction and aeronautics, and indicate a path toward even higher temperatures with continued design optimization and interconnect/material advances.

Abstract

Some applications require electronic systems to operate at extremely high temperature. Extending the operating temperature range of automotive-grade CMOS processes -- through the use of dedicated design techniques -- can provide an important cost-effective advantage. We present a second-order discrete-time delta-sigma analog-to-digital converter operating at a temperature of up to 250 C, well beyond the 175 C qualification temperature of the automotive-grade CMOS process used for its fabrication (XFAB XT018). The analog-to-digital converter incorporates design techniques that are effective in mitigating the adverse effects of the high temperature, such as increased leakage currents and electromigration. We use configurations of dummy transistors for leakage compensation, clock-boosting methods to limit pass-gate cross-talk, and we optimized the circuit architecture to ensure stability and accuracy at high temperature. Comprehensive measurements demonstrate that the analog-to-digital converter achieves a signal-to-noise ratio exceeding 93 dB at 250 C, with an effective number of bits of 12, and a power consumption of only 44~mW. The die area of the converter is only 0.065~mm and the area overhead of the high-temperature mitigation circuits is only 13.7%. The Schreier Figure of Merit is 140~dB at the maximum temperature of 250 C, proving the potential of the circuit for reliable operation in challenging applications such as gas and oil extraction and aeronautics.
Paper Structure (7 sections, 6 figures, 1 table)

This paper contains 7 sections, 6 figures, 1 table.

Figures (6)

  • Figure 1: Available ICs manufacturing technologies match the temperature ratings of different applications. Data extracted from Ref. Neudeck2002Shaddock2015Werner2001.
  • Figure 2: ADC architecture schematic overview: (a) 2nd-order DT Delta-Sigma modulator; (b) StrongArm latch comparator for bitstream signal output and single-bit DAC for feedback; (c) Folded-cascode operational amplifier used in the integrators, with junction leakage compensation method for single PMOS (p-type) and NMOS (n-type), and for the differential input pair. The dynamic CMFB circuit is shown in the same subpicture, providing the bias voltage VCMFB for the cascode amplifier, based on leakage-compensated pass-gates (PG).
  • Figure 3: Design techniques for leakage current reduction: (a) Pass-gate circuit with four dummy transistors (on the corners) for junction leakage compensation; (b) Two-phases clock boosting generator circuit; (c) Junction leakage current dependence on temperature and compensation with dummy devices; (d) Channel leakage current dependence on temperature and clock boosting.
  • Figure 4: Chip top view and layout magnification on the ADC block.
  • Figure 5: Measurement set-up for ADC characterization in the temperature range -40°C$\div$260°C: (a) Ceramic PCB for chip connection, compatible with the DIL48 package; (b) Connection wires between the ceramic PCB placed inside the oven and the measurement instruments outside it, rated for high temperature and with a custom metal shield for noise reduction; (c) Lab oven for high-temperature measurements up to 260°C, containing the chip with several instruments connected; (d) Climate chamber for low-temperature measurements up to -40°C.
  • ...and 1 more figures