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AGON: Automated Design Framework for Customizing Processors from ISA Documents

Chongxiao Li, Di Huang, Pengwei Jin, Tianyun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Xing Hu, Qi Guo

TL;DR

This paper tackles the challenge of automatically designing highly efficient customized processors with minimal human effort. It proposes AGON, a framework that uses an ISA-derived nano-operator (nOP) function intermediate representation to express functionality while decoupling it from optimization, enabling multi-level design (instruction, ISA, processor) and PPA-aware auto-tuning. Through a detailed suite of primitives and an LLM-driven nOP generation pipeline, AGON demonstrates competitive RTL prototypes with correctness guarantees and achieves an average $2.35\times$ speedup over a BOOM baseline while reducing design effort. The approach offers a practical infrastructure for rapid prototyping and evaluation of domain-specific OoO processors in the LLM era, with strong potential to accelerate hardware design and exploration. Key contributions include the nOP IR, a set of scheduling primitives, and an end-to-end framework for automated RTL generation from ISA documents, validated by extensive experiments and comparisons to existing LLM-assisted methods.

Abstract

Customized processors are attractive solutions for vast domain-specific applications due to their high energy efficiency. However, designing a processor in traditional flows is time-consuming and expensive. To address this, researchers have explored methods including the use of agile development tools like Chisel or SpinalHDL, high-level synthesis (HLS) from programming languages like C or SystemC, and more recently, leveraging large language models (LLMs) to generate hardware description language (HDL) code from natural language descriptions. However, each method has limitations in terms of expressiveness, correctness, and performance, leading to a persistent contradiction between the level of automation and the effectiveness of the design. Overall, how to automatically design highly efficient and practical processors with minimal human effort remains a challenge. In this paper, we propose AGON, a novel framework designed to leverage LLMs for the efficient design of out-of-order (OoO) customized processors with minimal human effort. Central to AGON is the nano-operator function (nOP function) based Intermediate Representation (IR), which bridges high-level descriptions and hardware implementations while decoupling functionality from performance optimization, thereby providing an automatic design framework that is expressive and efficient, has correctness guarantees, and enables PPA (Power, Performance, and Area) optimization. Experimental results show that superior to previous LLM-assisted automatic design flows, AGON facilitates designing a series of customized OoO processors that achieve on average 2.35 $\times$ speedup compared with BOOM, a general-purpose CPU designed by experts, with minimal design effort.

AGON: Automated Design Framework for Customizing Processors from ISA Documents

TL;DR

This paper tackles the challenge of automatically designing highly efficient customized processors with minimal human effort. It proposes AGON, a framework that uses an ISA-derived nano-operator (nOP) function intermediate representation to express functionality while decoupling it from optimization, enabling multi-level design (instruction, ISA, processor) and PPA-aware auto-tuning. Through a detailed suite of primitives and an LLM-driven nOP generation pipeline, AGON demonstrates competitive RTL prototypes with correctness guarantees and achieves an average speedup over a BOOM baseline while reducing design effort. The approach offers a practical infrastructure for rapid prototyping and evaluation of domain-specific OoO processors in the LLM era, with strong potential to accelerate hardware design and exploration. Key contributions include the nOP IR, a set of scheduling primitives, and an end-to-end framework for automated RTL generation from ISA documents, validated by extensive experiments and comparisons to existing LLM-assisted methods.

Abstract

Customized processors are attractive solutions for vast domain-specific applications due to their high energy efficiency. However, designing a processor in traditional flows is time-consuming and expensive. To address this, researchers have explored methods including the use of agile development tools like Chisel or SpinalHDL, high-level synthesis (HLS) from programming languages like C or SystemC, and more recently, leveraging large language models (LLMs) to generate hardware description language (HDL) code from natural language descriptions. However, each method has limitations in terms of expressiveness, correctness, and performance, leading to a persistent contradiction between the level of automation and the effectiveness of the design. Overall, how to automatically design highly efficient and practical processors with minimal human effort remains a challenge. In this paper, we propose AGON, a novel framework designed to leverage LLMs for the efficient design of out-of-order (OoO) customized processors with minimal human effort. Central to AGON is the nano-operator function (nOP function) based Intermediate Representation (IR), which bridges high-level descriptions and hardware implementations while decoupling functionality from performance optimization, thereby providing an automatic design framework that is expressive and efficient, has correctness guarantees, and enables PPA (Power, Performance, and Area) optimization. Experimental results show that superior to previous LLM-assisted automatic design flows, AGON facilitates designing a series of customized OoO processors that achieve on average 2.35 speedup compared with BOOM, a general-purpose CPU designed by experts, with minimal design effort.
Paper Structure (25 sections, 4 equations, 8 figures, 7 tables, 1 algorithm)

This paper contains 25 sections, 4 equations, 8 figures, 7 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Customized Processors
  4. Automated Processor Design Techniques
  5. LLM-based Attempts on Hardware Generation
  6. AGON Overview
  7. Functionality Descriptions in AGON
  8. Primitives in AGON
  9. Instruction-level Primitives
  10. ISA-level Primitives
  11. Processor-level Primitives
  12. Multi-level Verification
  13. Synthesize to RTL
  14. LLM-based AGON Generation
  15. Few-shot Learning
  16. ...and 10 more sections

Figures (8)

  • Figure 1: Comparing AGON with existing synthesis work in terms of needed expert effort and (a) complexity, (b) automation level.
  • Figure 2: The overview of AGON. (a) AGON decouples optimization from functionality, using nOP functions to describe the processor functionality, and then instantiates, optimizes, and verifies designs at different levels through a set of primitives. (b) An example of using AGON for design. The functional descriptions are generated with LLM. (c) The ISA document provided to LLM for the sha512sum0 instruction in (b). This snippet is taken from riscv_crypto, which originally contains natural language descriptions and pseudo code.
  • Figure 3: Concepts and examples about nOPs, nOP functions and nOP dataflow graphs. The nOPs in (b) correspond to the operations described in the natural language document in (a), and can be combined to form the nOP function in (c), and the dataflow is shown in (d).
  • Figure 4: Fusing nOPs with instruction.fuse primitive. (a) The original nOP dataflow graph of instruction sha512sum0. The minimum instruction execution cycle delay is 4 cycles. (b) After fusing with two patterns ror and xor3, the delay is reduced to 2 cycles.
  • Figure 5: The AGON's nOP function generation method. After the nOP functions are generated, they are sent for AGON's scheduling.
  • ...and 3 more figures