Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing

TL;DR

This work investigates neural computation implemented directly in-memory on memristive substrates to reduce data movement and energy costs. It combines in-memory inference, local online learning (e-prop and delta-rule based updates), and scalable routing within analog crossbar architectures, including PCM and perovskite memristors, to realize robust online learning and temporal credit assignment. The contributions span four core advances: bit-precision enhancement for binary memristors enabling on-chip learning; framework and hardware validation for online RSNN training with PCM/volatile devices and scalable eligibility traces (PCM-trace); discovery of reconfigurable halide perovskite memristors supporting volatile and non-volatile switching with RC demonstrations; and Mosaic, a small-world, analog systolic architecture that fuses in-memory computation with efficient routing. Together, these pieces demonstrate economically viable online learning on memristive substrates and establish pathways toward scalable, energy-efficient edge neuromorphic systems with hardware-aware training and routing.

Abstract

As neural computation is revolutionizing the field of Artificial Intelligence (AI), rethinking the ideal neural hardware is becoming the next frontier. Fast and reliable von Neumann architecture has been the hosting platform for neural computation. Although capable, its separation of memory and computation creates the bottleneck for the energy efficiency of neural computation, contrasting the biological brain. The question remains: how can we efficiently combine memory and computation, while exploiting the physics of the substrate, to build intelligent systems? In this thesis, I explore an alternative way with memristive devices for neural computation, where the unique physical dynamics of the devices are used for inference, learning and routing. Guided by the principles of gradient-based learning, we selected functions that need to be materialized, and analyzed connectomics principles for efficient wiring. Despite non-idealities and noise inherent in analog physics, I will provide hardware evidence of adaptability of local learning to memristive substrates, new material stacks and circuit blocks that aid in solving the credit assignment problem and efficient routing between analog crossbars for scalable architectures.

Figures (64)

• Figure 1: Importance of data locality is shown in the memory hierarchy as the computation (8b multiplication) costs only the fraction of the energy of memory access, in 45nm CMOS Horowitz2014-bn.
• Figure 2: Bias and variance in learning rules which estimate the gradients, even if they are not explicitly compute gradients. Figure taken from Richards_etal19.
• Figure 3: Mean and standard deviation of the device conductance as a function of the $I_{CC}$s. The inset shows the samples from the fitted mean and standard deviation used for the simulations.
• Figure 4: Event-based neuromorphic architecture using online learning in a 1T1R array (a), and the asynchronous state machine used as the switch controller applying the appropriate voltages on the BL, SL and WL of the array for online learning.
• Figure 5: Learning circuits generating the $I_{CC}$ for updating the devices based on the distance between the neuron and its target frequency. Highlighted in red is the Gm-C filters, low pass filtering the neuron and target spikes giving rise to $V_N$ and $V_T$. In green and orange, the error between the two is calculated generating positive ($I_{ErrP}$) and negative ($I_{ErrN}$) errors, unless error is small and STOP signal is high. In purple, $V_e$, the excitatory voltage from Fig.\ref{['fig:arch']}, regenerates the read current and is scaled to $I_{scale}$ producing $I_{e_S}$. Based on the error sign (UP), $I_{CC1}$ is either the sum of $I_{e_S}$ and $I_{Err}$ or the subtraction of the two.