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Entropy Density Benchmarking of Near-Term Quantum Circuits

Marine Demarty, James Mills, Kenza Hammam, Raul Garcia-Patron

TL;DR

This work introduces entropy-density benchmarking as a bridge between circuit- and application-level benchmarking for NISQ devices. It develops a simple global depolarizing heuristic to model entropy accumulation in variational quantum circuits, validates it against classical-simulation and experimental data, and refines it with T1-relaxation effects. By combining this entropy-accumulation model with an application-level quantum-advantage framework, the authors derive tighter circuit-size bounds that delineate where quantum advantage is still feasible, demonstrating practical implications for MAX-CUT on superconducting hardware. The study highlights both the promise of entropy-based benchmarks and the need for more sophisticated noise models and error-mitigation strategies to tighten predictions for larger systems and diverse platforms.

Abstract

Understanding the limitations imposed by noise on current and next-generation quantum devices is a crucial step towards demonstrating practical quantum advantage. In this work, we investigate the accumulation of entropy density as a benchmark to monitor the performance of quantum processing units. We provide a proof-of-principle demonstration of our novel methodology which entails developing simple heuristic models of how entropy accumulates, testing them against real QPU experiments, and finally using these models to determine a circuit volume threshold above which quantum advantage is unattainable. Monitoring entropy density not only offers a novel approach that complements existing circuit-level benchmarking techniques, but more importantly, it bridges the gap between circuit-level and application-level benchmarking protocols. In particular, our heuristic model of entropy accumulation allows us to outperform existing techniques that bound the circuit size threshold for quantum advantage.

Entropy Density Benchmarking of Near-Term Quantum Circuits

TL;DR

This work introduces entropy-density benchmarking as a bridge between circuit- and application-level benchmarking for NISQ devices. It develops a simple global depolarizing heuristic to model entropy accumulation in variational quantum circuits, validates it against classical-simulation and experimental data, and refines it with T1-relaxation effects. By combining this entropy-accumulation model with an application-level quantum-advantage framework, the authors derive tighter circuit-size bounds that delineate where quantum advantage is still feasible, demonstrating practical implications for MAX-CUT on superconducting hardware. The study highlights both the promise of entropy-based benchmarks and the need for more sophisticated noise models and error-mitigation strategies to tighten predictions for larger systems and diverse platforms.

Abstract

Understanding the limitations imposed by noise on current and next-generation quantum devices is a crucial step towards demonstrating practical quantum advantage. In this work, we investigate the accumulation of entropy density as a benchmark to monitor the performance of quantum processing units. We provide a proof-of-principle demonstration of our novel methodology which entails developing simple heuristic models of how entropy accumulates, testing them against real QPU experiments, and finally using these models to determine a circuit volume threshold above which quantum advantage is unattainable. Monitoring entropy density not only offers a novel approach that complements existing circuit-level benchmarking techniques, but more importantly, it bridges the gap between circuit-level and application-level benchmarking protocols. In particular, our heuristic model of entropy accumulation allows us to outperform existing techniques that bound the circuit size threshold for quantum advantage.

Paper Structure

This paper contains 36 sections, 53 equations, 9 figures, 2 tables.

Figures (9)

  • Figure 1: First two circuit layers of a 5-qubit hardware-efficient parameterized quantum circuit $U(\Vec{\theta})$. Each circuit layer is composed of a single-qubit $R_X(\theta)$ rotation followed by a $R_Y(\theta)$ rotation and a final layer of $CZ$ gates between nearest neighbours. The angles $\theta_i$s are drawn from the uniform distribution over $[0,2\pi)$.
  • Figure 2: Numerical simulation and heuristic model. We simulate a single VQA circuit represented in Fig. \ref{['fig:ideal_hardware_efficient_param_circuit']}, with randomly selected parameters (random seed np.random.seed(837)) affected by local depolarizing noise ($p_1=0.008$ and $p_2=0.054$ from calibration data of Rigetti's QPU, Aspen-M-3). The dots characterise the Renyi-2 entropy density evolution of the quantum register after each circuit layer for different number of qubits $n$ (see colour label). The black horizontal dash-dotted line corresponds to the entropy density of the maximally mixed state $\sigma_0\coloneqq I/2^n$. The solid lines correspond to interpolations using a global depolarizing heuristic model from Eq. \ref{['eq:purity-model-from-class-sim']} with fitting parameters $\alpha_1$ and $\alpha_2$ ($\alpha_i\approx p_i$), as detailed in subsection \ref{['subsubsec:analytical-model']}.
  • Figure 3: Classical shadows protocol. Each $V_i$ is a single-qubit Clifford gate such that its combination with a computational basis measurement corresponds to a random measurement in the $X$, $Y$, or $Z$ basis.
  • Figure 4: Experimental results and validation of our heuristic model. We consider a VQA circuit as in Fig. \ref{['fig:ideal_hardware_efficient_param_circuit']} applied to $n=3$ qubits, with fixed circuit parameters (fixed random seed np.random.seed(837)). Golden error bars give the purity and Renyi-2 entropy evolution as functions of circuit depth on Rigetti's QPU Aspen-M-3 using two different methods. Each error bar was obtained by running the classical shadows protocol $3$ times, and computing the average estimate and the standard deviation over those $3$ samples. Results obtained in the same setting but using a local depolarizing noise model ($p_1=0.008$ and $p_2=0.054$ from calibration data of Aspen-M-3) and without measurement errors correspond to the light blue error bars. The dark blue error bars in Fig. \ref{['subfig:QPU_run_n=3-R2d']} correspond to the same simulation with added measurement errors from calibration data (measurement circuit gate errors $p_1=0.008$ and errors in the detectors $P(0|1)=0.03$ and $P(1|0)=0.02$). The dark blue error bars in Fig. \ref{['subfig:QPU_run_n=3-R2d-T1']} also include $T_1$ relaxation errors both at the gate level ($\gamma_1, \gamma_2 = 0.003, 0.015$) right after depolarization ($p_1, p_2 = 0.006, 0.038$) and in the measurement stage ($\gamma_{meas}=0.05$) just before readout errors ($P(0|1)=P(1|0)=0.03$) based on calibration data. The black solid lines show the purity and Renyi-2 entropy density evolution obtained via density matrix simulation under our local depolarizing noise model without measurement errors (similar to light blue error bars). The black horizontal dash-dotted lines correspond to the purity or entropy density of the maximally mixed state $\sigma_0\coloneqq I/2^n$. Fit of our global depolarizing heuristic model, where we have imposed that $\alpha_2/\alpha_1=p_2/p_1$, and where $\beta$ models readout errors and noise in the measurement circuit, corresponds to the solid golden and blue lines.
  • Figure 5: Quantum advantage benchmarking framework from stilck_franca_limitations_2021. For an optimization task of the form $\min_{\rho} Tr[H\rho]$, the authors derive a lower bound (blue solid line) on the quantum device's solution to the energy density ($\mathop{\mathrm{Tr}}\nolimits[H\rho_{out}]/n$) as a function of the accumulated entropy density ($S(\rho_{out})/n$). The state-of-the-art classical solvers' solution to this optimization problem (red horizontal line) defines an entropy density threshold $c$ such that if the quantum device's candidate solution $\rho_{out}$ satisfies $\frac{S(\rho_{out})}{n} \geq c$ then quantum advantage is out of reach for this device and for this optimization problem.
  • ...and 4 more figures