TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering

TL;DR

TNNGen introduces an automated framework that bridges PyTorch-based temporal neural networks with post-layout hardware implementations for neuromorphic sensory processing units. The system combines a PyTorch functional simulator for fast design-space exploration with a PyVerilog-based hardware generator to produce RTL and chip layouts, leveraging Cadence tools and TNN7 macros. Evaluations across seven UCR time-series clustering designs show favorable hardware metrics, substantial area and leakage reductions with 7nm macros, and near-real-time inference latency suitable for edge deployment, while also providing a silicon-forecasting capability to estimate area and power without full fabrication flows. This end-to-end approach significantly reduces manual hardware design effort and accelerates exploration of energy-efficient TNN-based NSPUs for online sensing tasks.

Abstract

Temporal Neural Networks (TNNs), a special class of spiking neural networks, draw inspiration from the neocortex in utilizing spike-timings for information processing. Recent works proposed a microarchitecture framework and custom macro suite for designing highly energy-efficient application-specific TNNs. These recent works rely on manual hardware design, a labor-intensive and time-consuming process. Further, there is no open-source functional simulation framework for TNNs. This paper introduces TNNGen, a pioneering effort towards the automated design of TNNs from PyTorch software models to post-layout netlists. TNNGen comprises a novel PyTorch functional simulator (for TNN modeling and application exploration) coupled with a Python-based hardware generator (for PyTorch-to-RTL and RTL-to-Layout conversions). Seven representative TNN designs for time-series signal clustering across diverse sensory modalities are simulated and their post-layout hardware complexity and design runtimes are assessed to demonstrate the effectiveness of TNNGen. We also highlight TNNGen's ability to accurately forecast silicon metrics without running hardware process flow.

Figures (4)

• Figure 1: The TNNGen framework for designing TNN-based neuromorphic sensory processing units. It comprises a PyTorch functional simulator and a hardware generator, and automates the entire design flow from PyTorch to chip layout.
• Figure 2: Layouts of three generated column configurations fitted onto the same floorplan size. $p\times q$ column configurations are provided with computation latencies inside parentheses.
• Figure 3: Innvous place-and-route runtime (in seconds) for baseline (ASAP7) and TNNGen (TNN7) column designs.
• Figure 4: Area and Leakage power forecasting illustrating actual data points ('stars') and the forecasting trendline equations.