Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Tiered Acquisition for Constrained Bayesian Optimization: An Application to Analog Circuits

Ria Rashid, Abhishek Gupta

TL;DR

The paper tackles constrained Bayesian optimization for analog circuit design by introducing TRACE, a tiered acquisition ensemble with two dominance levels that first emphasizes feasibility and then optimizes within the feasible set. TRACE defines constraint-aware acquisition functions and leverages Gaussian Process surrogates to navigate highly constrained search spaces, using a two-level Pareto dominance to guide selection. Applied to a 65nm two-stage Miller compensated operational amplifier, TRACE achieves substantial improvements in gain and area while substantially reducing constraint violations compared with state-of-the-art alternatives, with reported gains up to 43% and area reductions up to 33%. The method is implemented in Python with Ngspice, and the results demonstrate TRACE's potential to enhance automation and reliability in analog circuit design under tight specifications.

Abstract

Analog circuit design can be considered as an optimization problem with the targeted circuit specifications as constraints. When stringent circuit specifications are considered, it is desired to have an optimization methodology that adapts well to heavily constrained search spaces. To this end, we propose a novel Bayesian optimization algorithm with a tiered ensemble of acquisition functions and demonstrate its considerable application potential for analog circuit design automation. Our method is the first to introduce the concept of multiple dominance among acquisition functions, allowing the search for the optimal solutions to be effectively bounded \emph{within} the predicted set of feasible solutions in a constrained search space. This has resulted in a significant reduction in constraint violations by the candidate solutions, leading to better-optimized designs within tight computational budgets. The methodology is validated in gain and area optimization of a two-stage Miller compensated operational amplifier in a 65 nm technology. In comparison to robust baselines and state-of-the-art algorithms, this method reduces constraint violations by up to 38% and improves the target objective by up to 43%. The source code of our algorithm is made available at https://github.com/riarashid/TRACE.

Tiered Acquisition for Constrained Bayesian Optimization: An Application to Analog Circuits

TL;DR

The paper tackles constrained Bayesian optimization for analog circuit design by introducing TRACE, a tiered acquisition ensemble with two dominance levels that first emphasizes feasibility and then optimizes within the feasible set. TRACE defines constraint-aware acquisition functions and leverages Gaussian Process surrogates to navigate highly constrained search spaces, using a two-level Pareto dominance to guide selection. Applied to a 65nm two-stage Miller compensated operational amplifier, TRACE achieves substantial improvements in gain and area while substantially reducing constraint violations compared with state-of-the-art alternatives, with reported gains up to 43% and area reductions up to 33%. The method is implemented in Python with Ngspice, and the results demonstrate TRACE's potential to enhance automation and reliability in analog circuit design under tight specifications.

Abstract

Analog circuit design can be considered as an optimization problem with the targeted circuit specifications as constraints. When stringent circuit specifications are considered, it is desired to have an optimization methodology that adapts well to heavily constrained search spaces. To this end, we propose a novel Bayesian optimization algorithm with a tiered ensemble of acquisition functions and demonstrate its considerable application potential for analog circuit design automation. Our method is the first to introduce the concept of multiple dominance among acquisition functions, allowing the search for the optimal solutions to be effectively bounded \emph{within} the predicted set of feasible solutions in a constrained search space. This has resulted in a significant reduction in constraint violations by the candidate solutions, leading to better-optimized designs within tight computational budgets. The methodology is validated in gain and area optimization of a two-stage Miller compensated operational amplifier in a 65 nm technology. In comparison to robust baselines and state-of-the-art algorithms, this method reduces constraint violations by up to 38% and improves the target objective by up to 43%. The source code of our algorithm is made available at https://github.com/riarashid/TRACE.

Paper Structure

This paper contains 14 sections, 1 theorem, 15 equations, 3 figures, 10 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Constrained Optimization Problem Formulation
  4. Bayesian Optimization
  5. Gaussian Processes (GP)
  6. Acquisition Functions
  7. Optimization with Multiple Dominance Levels
  8. TRACE
  9. Simulation results
  10. Test Functions
  11. Test Function 1:
  12. Test Function 2:
  13. Branin Function:
  14. Conclusion

Key Result

Proposition 1

Let $\vb*x\in \vb*X$ and $\mu_{ci}(\vb*x) = c_i(x)$$\forall i$. Then, the Pareto set expressed as $min(\vb*X,\preceq_{F1})$, where $F_1 = [f_{cv1}(\vb*x), f_{cv2}(\vb*x)]$, has a one-to-one correspondence to the entire feasible region.

Figures (3)

  • Figure 1: Schematic of the TSMCOA used in our simulations.
  • Figure 2: Comparison of mean convergence plots of MACE and TRACE for gain optimization.
  • Figure 3: Comparison of mean convergence plots of MACE and TRACE for area optimization.

Theorems & Definitions (2)

  • Proposition 1
  • proof