Characterisation of individual gates using twirling circuits
David Amaro-Alcalá
TL;DR
The paper introduces a fixed-circuit twirling method based on the supermap formalism to characterize single-qubit gates, achieving a twirl equivalent to averaging over $U(2)$ without random gate sequences. It constructs an explicit circuit using a coset decomposition of a unitary 2-design, yielding a $ ext{C}_2$-twirl implemented by a fixed gate sequence with auxiliary qudits, and presents a four-measurement protocol to extract the average gate fidelity of a target gate with precise sample bounds. A key result is $\Gamma(\mathcal{T}_{\mathsf{U}(2)}[\mathcal{E}]) = I_1 \oplus (1-p(\mathcal{E})) I_3$, and a practical estimator $1-p(G) = (q_0 - q_1)/(q_2 - q_3)$ with Hoeffding-based sample size. The method offers advantages over interleaved benchmarking by removing gate-noise assumptions, enabling straightforward confidence intervals, and scalable extension to qudits and other unitary 2-designs, thus broadening the toolkit for quantum gate benchmarking in multi-qubit devices.
Abstract
We present a method to characterise qubit gates. Utilising the supermap formalism, we create a scheme for deterministic single-qubit gate analysis. Our approach introduces a new twirling process that is applied directly through fixed circuits. This method removes the requirement to average over random gates. The results enhance randomised benchmarking techniques and are suitable for experimental setups with multi-qubit control, focusing on the precise characterisation of single-qubit gates.
