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Quantum SWAP gate realized with CZ and iSWAP gates in a superconducting architecture

Christian Križan, Janka Biznárová, Liangyu Chen, Emil Hogedal, Amr Osman, Christopher W. Warren, Sandoko Kosen, Hang-Xi Li, Tahereh Abad, Anuj Aggarwal, Marco Caputo, Jorge Fernández-Pendás, Akshay Gaikwad, Leif Grönberg, Andreas Nylander, Robert Rehammar, Marcus Rommel, Olga I. Yuzephovich, Anton Frisk Kockum, Joonas Govenius, Giovanna Tancredi, Jonas Bylander

TL;DR

This work addresses the need for a richer two-qubit gate set on superconducting qubits to improve circuit compilation. It proposes and experimentally demonstrates a SWAP decomposition into a single $iSWAP$ followed by a single $CZ$ gate, leveraging a fixed-frequency transmon architecture with a tunable coupler. The approach extends the native gate set so that any two-qubit Clifford unitary can be realized with at most two two-qubit gates plus single-qubit gates, and validates the CZ, $iSWAP$, and SWAP operations via cross-Ramsey spectroscopy with SPAM-mitigation. The results suggest potential reductions in circuit depth and gate time, with practical impact for NISQ-era algorithms and error-correction schemes, especially if parallel gate execution and shorter pulses can be realized.

Abstract

It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen with existing platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform's native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.

Quantum SWAP gate realized with CZ and iSWAP gates in a superconducting architecture

TL;DR

This work addresses the need for a richer two-qubit gate set on superconducting qubits to improve circuit compilation. It proposes and experimentally demonstrates a SWAP decomposition into a single followed by a single gate, leveraging a fixed-frequency transmon architecture with a tunable coupler. The approach extends the native gate set so that any two-qubit Clifford unitary can be realized with at most two two-qubit gates plus single-qubit gates, and validates the CZ, , and SWAP operations via cross-Ramsey spectroscopy with SPAM-mitigation. The results suggest potential reductions in circuit depth and gate time, with practical impact for NISQ-era algorithms and error-correction schemes, especially if parallel gate execution and shorter pulses can be realized.

Abstract

It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen with existing platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform's native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.

Paper Structure

This paper contains 21 sections, 19 equations, 13 figures, 2 tables.

Figures (13)

  • Figure 1: Derivation of the SWAP operation using CZ and iSWAP gates. (a) The SWAP gate is equivalent to three subsequent CNOT gates Mike_and_Ike, as is true also in classical logic. (b) The initial double-CNOT gate may be expressed using an iSWAP gate combined with conjugate-transposed phase gates ($S^\dagger$) and Hadamard ($H$) gates Crooks2023: $\mathrm{CNOT}_{10}(\mathrm{CNOT}_{01}(\Psi))$ is decompiled into its iSWAP equivalent. (c) We express the last $\mathrm{CNOT}_{01}$ gate from (a) as its local equivalent Zhang2004, using a CZ gate and by straddling one qubit with two $H$ gates. (d) We finally put (b) and (c) together to form a SWAP operation. Note here that the two subsequent $H$ gates cancel into identity, $H(H(\Psi)) = I(\Psi)$. In principle, the order of the CZ and iSWAP gates in (d) is irrelevant as they commute.
  • Figure 2: (a) Scale drawing of the energy-level diagram for our two-qubit system $\ket{Q_1\,Q_2}$, where the coupler remains in the ground state for all experiments. We indicate the native two-qubit gate interactions used in our experiments. (b) Two-tier flip chip quantum processor. (c) Device used in our experiments: the qubits and coupler are placed on the flip chip die, and the resonators are located on a silicon interposer Kosen2022Kosen2024. The interposer contains the signal wiring that provides charge to the qubits, labeled XY$_{\mathrm{1}}$ and XY$_{\mathrm{2}}$, and flux to the coupler, labeled Z. (d) Equivalent circuit-QED schematic of (c), with resonators highlighted in green, transmons highlighted in red, the coupler highlighted in turqoise along with its coupling strengths g, and signal wiring hightlighted in purple. See \ref{['appendix:experimental_setup']} for the full setup.
  • Figure 3: Ramsey sequences demonstrating the populations and phases resulting from the two-qubit CZ (a, d), iSWAP (b, e), and SWAP (c, f) gates. In the upper row of the measured data, the two-qubit gates were performed on the states $\ket{0\,\bar{i}}$ and $\ket{1\,\bar{i}}$, whereas in the lower row, the roles of qubits 1 and 2 were swapped. The data points are post-processed to mitigate state preparation and measurement (SPAM) errors; see \ref{['appendix:error_mitigation']}. The overlaid sinusoidal curves show the ideal outcome, and the dotted curves take $T_1$ relaxation into account. The CZ, iSWAP, and SWAP results were taken with 35,000 (bottom CZ: 10,000), 15,000 and 250,000 samples per data point respectively. The groups of data that significantly diverge from the ideal curves are discussed further in Section \ref{['sec:discussion']}. Blue-purple data points relate to conditional Ramsey experiments, while the red-green points relate to cross-Ramsey experiments. The mean squared error between the post-processed data and the ideal curves ranges between 0.001 and 0.020 at an average of 0.007, where the number of samples is 32 for the CZ data and 16 for the iSWAP and SWAP data. Supplementary post-processing data are available in \ref{['appendix:error_mitigation']}.
  • Figure 4: Our RF setup inside a Bluefors LD250 dilution refrigerator, similar to the suggested layout in Krinner2019. LPF, HPF, BPF, denotes low-, high-, and band-pass filters. AWG denotes an arbitrary waveform generator.
  • Figure 5: Time scatter data of decoherence parameters taken during 180 hours. The lack of many fit points for the $T_2^*$ data of $Q_1$ appears to capture this qubit's temporal erratic behavior, keeping in mind that each data point required about 10 min of measurement time. Sudden jumps in the data cause fit failures or error bars of more than 15%, which we enforce as a hard limit on acceptable fit error.
  • ...and 8 more figures