Quantum SWAP gate realized with CZ and iSWAP gates in a superconducting architecture
Christian Križan, Janka Biznárová, Liangyu Chen, Emil Hogedal, Amr Osman, Christopher W. Warren, Sandoko Kosen, Hang-Xi Li, Tahereh Abad, Anuj Aggarwal, Marco Caputo, Jorge Fernández-Pendás, Akshay Gaikwad, Leif Grönberg, Andreas Nylander, Robert Rehammar, Marcus Rommel, Olga I. Yuzephovich, Anton Frisk Kockum, Joonas Govenius, Giovanna Tancredi, Jonas Bylander
TL;DR
This work addresses the need for a richer two-qubit gate set on superconducting qubits to improve circuit compilation. It proposes and experimentally demonstrates a SWAP decomposition into a single $iSWAP$ followed by a single $CZ$ gate, leveraging a fixed-frequency transmon architecture with a tunable coupler. The approach extends the native gate set so that any two-qubit Clifford unitary can be realized with at most two two-qubit gates plus single-qubit gates, and validates the CZ, $iSWAP$, and SWAP operations via cross-Ramsey spectroscopy with SPAM-mitigation. The results suggest potential reductions in circuit depth and gate time, with practical impact for NISQ-era algorithms and error-correction schemes, especially if parallel gate execution and shorter pulses can be realized.
Abstract
It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen with existing platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform's native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.
