Event-based backpropagation on the neuromorphic platform SpiNNaker2

TL;DR

This work addresses the challenge of training deep spiking neural networks efficiently on neuromorphic hardware by implementing exact, event-based backpropagation (EventProp) directly on SpiNNaker2. The approach uses four on-chip programs to perform forward computation, backward adjoint propagation, loss computation, and gradient-based weight updates, with batch-parallel execution to leverage the hardware's inherent parallelism. A Yin Yang classification task demonstrates successful on-chip training with strong correspondence to an off-chip PyTorch simulator, while profiling highlights substantial energy efficiency relative to GPU-based implementations. The results suggest that event-based training on neuromorphic substrates can enable real-time learning and scalable, energy-efficient adaptation for edge devices, with potential extensions to hybrid online–offline and meta-learning workflows using off-chip optimization to bootstrap on-chip learning.

Abstract

Neuromorphic computing aims to replicate the brain's capabilities for energy efficient and parallel information processing, promising a solution to the increasing demand for faster and more efficient computational systems. Efficient training of neural networks on neuromorphic hardware requires the development of training algorithms that retain the sparsity of spike-based communication during training. Here, we report on the first implementation of event-based backpropagation on the SpiNNaker2 neuromorphic hardware platform. We use EventProp, an algorithm for event-based backpropagation in spiking neural networks (SNNs), to compute exact gradients using sparse communication of error signals between neurons. Our implementation computes multi-layer networks of leaky integrate-and-fire neurons using discretized versions of the differential equations and their adjoints, and uses event packets to transmit spikes and error signals between network layers. We demonstrate a proof-of-concept of batch-parallelized, on-chip training of SNNs using the Yin Yang dataset, and provide an off-chip implementation for efficient prototyping, hyper-parameter search, and hybrid training methods.

Figures (4)

• Figure 1: Software and Hardware stack: A.1 shows the software architecture stack. The host experiment runner handles network creation, simulation parameters, initial data and mapping, all of which are detailed in A.2. Necessary data is then sent on-chip. B. details the 4 main programs responsible for executing the eventprop algorithm on-chip, detailed later on. C. shows a potential mapping of a multi-batch simulation on the SpiNNaker2 chip.
• Figure 2: Yin Yang Dataset: Left-hand side shows true coordinates coloured by labels, while right-hand side shows the time steps of discretized spike-times.
• Figure 3: Accuracy comparison between on- and off-chip simulations. On the left, we show the final accuracy of the models after training for 40 epochs on the complete dataset, for both testing and training sets. On the right we show the final accuracies reached in the "online" setting, after only seeing 300 samples one by one. Results are displayed using a standard boxplot, displaying the median (labelled) and quartiles values of the distribution. All individual points are also overlayed on top.
• Figure 4: Voltage differences of the on-chip and off-chip implementations after processing a single sample.