Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology

TL;DR

This work addresses the temperature sensitivity of analog neuromorphic circuits by introducing a dynamic read-voltage compensation scheme for weight storage and VMM operation, enabling a two-layer analog neural network to operate accurately from $10^{\circ}\mathrm{C}$ to $60^{\circ}\mathrm{C}$ on a single-poly $180\,\mathrm{nm}$ CMOS process. The authors implement two $16\times16$ time-domain VMMs with 1T-FG floating-gate memories, achieving $ENOB$ around $4.7$ bits for weights and $5.7$ bits for outputs, and map signed weights through a dual-branch scheme. The key contribution is an adaptive $V_{\rm READ}$ rule, $\Delta V_{\rm READ}/\Delta T \approx -3$ mV/°C, which mitigates first-order magnification and partially corrects higher-order distortions, preserving classification accuracy within $2\%$ of software across the tested temperature range. Experimental results on a low-resolution MNIST-like task show sustained accuracy (~$83\%$) with temperature, and memory retention is demonstrated with a feasible refresh strategy. This approach demonstrates the viability of low-cost CMOS processes for energy-efficient analog neuromorphic inference in edge devices. The work significantly advances practical AIMC by combining in-memory analog computing with temperature-aware compensation, enabling robust, low-power neuromorphic chips at scale.

Abstract

In analog neuromorphic chips, designers can embed computing primitives in the intrinsic physical properties of devices and circuits, heavily reducing device count and energy consumption, and enabling high parallelism, because all devices are computing simultaneously. Neural network parameters can be stored in local analog non-volatile memories (NVMs), saving the energy required to move data between memory and logic. However, the main drawback of analog sub-threshold electronic circuits is their dramatic temperature sensitivity. In this paper, we demonstrate that a temperature compensation mechanism can be devised to solve this problem. We have designed and fabricated a chip implementing a two-layer analog neural network trained to classify low-resolution images of handwritten digits with a low-cost single-poly complementary metal-oxide-semiconductor (CMOS) process, using unconventional analog NVMs for weight storage. We demonstrate a temperature-resilient analog neuromorphic chip for image recognition operating between 10$^{\circ}$C and 60$^{\circ}$C without loss of classification accuracy, within 2\% of the corresponding software-based neural network in the whole temperature range.

Figures (8)

• Figure 1: Multi-layer fabricated neural network. (a) Architecture of the multi-layer neural network performing image classification on a low-resolution ($4\times4$) version of MNIST database, with detail of the mapped weights on the two TD-VMMs used in the hidden and output fully-connected layers; (b) architecture and layout of the designed analog $16\times16$ time-domain VMM, with details of row and column decoders and drivers, input-to-pulse converter, charge amplifiers and NVM FG cell matrix; (c) sketch of the physical phenomena involved when writing (hot electron injection) or erasing (impact-ionisation hot hole injection) a 1T-FG cell; (d) the fabricated chip was packaged and tested using a custom PCB and commercial development kit.
• Figure 2: TD-VMM operation and precision characterisation: (a) Detail of the MAC operations performed by a column (BL) of the TD-VMM; (b) timing diagram of the VMM operation; (c) spatial map of the native weights of a typical $16\times16$ crossbar array (random pulse-width input vector distribution shown in the inset); (d) histograms of the measured and theoretical VMM outputs for a given set of random input data, with (e) corresponding scatter plot of measured vs. theoretical outputs (f) and extracted output errors ($\text{ERR}= \Delta V_{\rm OUT,EXP}-\Delta V_{\rm OUT,REF}$); (g) ENOB extracted for each BL column of three different dies.
• Figure 3: Flowchart of the tools and techniques used in the present work.
• Figure 4: Programmed Weights. Hidden Layer: spatial maps of the (a) experimental 1T-weights and (b) corresponding $\Delta W = W_{\rm EXP} - W_{\rm TGT}$ and (c) related error histogram. Output Layer: spatial maps of the (d) experimental 1T-weights and (e) corresponding $\Delta W$ and (f) related error histogram. Scatter plots of $1T-W_{\rm EXP}$ (hidden+output layers) with respect to $1T-W_{\rm TGT}$ as a function of (g) temperature and of (h)$V_{\rm READ}$. (j) Weight magnification and (k) ENOB as a function of temperature and $V_{\rm READ}$. 2T-weight dependence of the temperature under (i) constant $V_{\rm READ}$ and (l)$V_{\rm READ}$ correction conditions.
• Figure 5: Low-resolution digit classification. Confusion matrices extracted under constant $V_{\rm READ}$ and adaptive $V_{\rm{READ}}$ tests at 10$^{\circ}$C ((a) and (b), respectively) and 60$^{\circ}$C ((c) and (d), respectively). Corresponding normalized histograms (in probability distribution function form) of the output-layer TD-VMM outputs under (e) constant $V_{\rm READ}$ and (f)$V_{\rm READ}$ correction tests. (g) Classification accuracy against temperature. Degradation over time of the (h) weight ENOB and of the (i) network classification accuracy.