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T-Edge: Trusted Heterogeneous Edge Computing

Jiamin Shen, Yao Chen, Weng-Fai Wong, Ee-Chien Chang

TL;DR

This work addresses security and privacy challenges in edge computing with heterogeneous ARM/FPGA platforms by introducing T-Edge, a practical trusted execution environment that combines ARM TrustZone isolation with FPGA fabric. It defines a three-stage lifecycle (manufacture, provisioning, operation), introduces a remote attestation protocol with boot-time measurements and runtime challenge-response, and ensures a secure, isolated CPU-FPGA channel alongside controlled FPGA reconfiguration. The approach is validated through a prototype on a Xilinx ZCU106 board, a formal verification of the protocol with ProVerif, and a case study using a 2D convolution accelerator, showing negligible runtime overhead and a modest boot-time increase. The solution provides device and program authentication, secure channels, and attestation privacy, offering a viable path for trusted, FPGA-accelerated edge computing in cloud and on-premises deployments.

Abstract

Heterogeneous computing, which incorporates GPUs, NPUs, and FPGAs, is increasingly utilized to improve the efficiency of computer systems. However, this shift has given rise to significant security and privacy concerns, especially when the execution platform is remote. One way to tackle these challenges is to establish a trusted and isolated environment for remote program execution, while maintaining minimal overhead and flexibility. While CPU-based trusted execution has been extensively explored and found commercial success, extension to heterogeneous computing systems remains a challenge. This paper proposes a practical trusted execution environment design for ARM/FPGA System-on-Chip platforms, leveraging TrustZone's unique characteristics. The design features a dedicated security controller within the ARM TrustZone, overseeing FPGA reconfiguration and managing communication between CPU cores and FPGA fabrics. This design involves a provisioning service that enables application users to establish trust in the FPGA fabric within cloud-based computing resources provided by the platform owner, running applications developed by third-party developers and hardware manufactured by the device manufacturer. To ensure the security of our proposed system, we employ an automated protocol verifier, ProVerif, to validate its compliance with essential security requirements. Furthermore, we demonstrate the practicality of our system model by implementing a prototype application on the Xilinx MPSoC development board.

T-Edge: Trusted Heterogeneous Edge Computing

TL;DR

This work addresses security and privacy challenges in edge computing with heterogeneous ARM/FPGA platforms by introducing T-Edge, a practical trusted execution environment that combines ARM TrustZone isolation with FPGA fabric. It defines a three-stage lifecycle (manufacture, provisioning, operation), introduces a remote attestation protocol with boot-time measurements and runtime challenge-response, and ensures a secure, isolated CPU-FPGA channel alongside controlled FPGA reconfiguration. The approach is validated through a prototype on a Xilinx ZCU106 board, a formal verification of the protocol with ProVerif, and a case study using a 2D convolution accelerator, showing negligible runtime overhead and a modest boot-time increase. The solution provides device and program authentication, secure channels, and attestation privacy, offering a viable path for trusted, FPGA-accelerated edge computing in cloud and on-premises deployments.

Abstract

Heterogeneous computing, which incorporates GPUs, NPUs, and FPGAs, is increasingly utilized to improve the efficiency of computer systems. However, this shift has given rise to significant security and privacy concerns, especially when the execution platform is remote. One way to tackle these challenges is to establish a trusted and isolated environment for remote program execution, while maintaining minimal overhead and flexibility. While CPU-based trusted execution has been extensively explored and found commercial success, extension to heterogeneous computing systems remains a challenge. This paper proposes a practical trusted execution environment design for ARM/FPGA System-on-Chip platforms, leveraging TrustZone's unique characteristics. The design features a dedicated security controller within the ARM TrustZone, overseeing FPGA reconfiguration and managing communication between CPU cores and FPGA fabrics. This design involves a provisioning service that enables application users to establish trust in the FPGA fabric within cloud-based computing resources provided by the platform owner, running applications developed by third-party developers and hardware manufactured by the device manufacturer. To ensure the security of our proposed system, we employ an automated protocol verifier, ProVerif, to validate its compliance with essential security requirements. Furthermore, we demonstrate the practicality of our system model by implementing a prototype application on the Xilinx MPSoC development board.

Paper Structure

This paper contains 44 sections, 1 equation, 6 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Trusted Execution Environment (TEE)
  4. Existing CPU-based TEE
  5. Field-Programmable Gate Array (FPGA)
  6. Existing FPGA Security Enforcement
  7. ARM/FPGA SoC
  8. Boot Process and Secure Boot
  9. Framework Formulation
  10. System Model
  11. Manufacture Stage
  12. Provisioning Stage
  13. Operational Stage
  14. Threat Model
  15. Device Manufacturer ($\mathcal{M}$)
  16. ...and 29 more sections

Figures (6)

  • Figure 1: Pairing CPU-based TEE with FPGA. The FPGA fabric needs to be involved in the trust boundary. It's essential to secure the link between the CPU and FPGA.
  • Figure 2: Comparison between the architectures of Intel SGX and ARM TrustZone. The shaded blocks represent the trusted components.
  • Figure 3: Simplified Boot Sequence of the System. The Boot ROM is an unmodifiable piece of code embedded in the chip.
  • Figure 4: System Model
  • Figure 5: Attestation Protocol
  • ...and 1 more figures