AI-Powered Algorithm-Centric Quantum Processor Topology Design

TL;DR

This work tackles the problem of quantum circuit compilation by co-designing the processor topology to optimize performance on NISQ devices. It introduces Qtailor, an RL-based framework that jointly designs topology under restricted connectivity and maps circuits, guided by a depth-oriented reward. A key innovation is Reward-Replay PPO (RR-PPO), which reuses action rewards to speed up training, and a force-directed grid layout that aligns topology with manufacturability. Empirically, QTailor achieves up to 46% circuit-depth reductions in 60% of cases and shows stronger benefits as circuit size grows, while maintaining compatibility with existing compilers like Qiskit and Sabre. This approach demonstrates a promising pathway for co-designing quantum processor architectures and algorithm mapping to improve fidelity and scalability.

Abstract

Quantum computing promises to revolutionize various fields, yet the execution of quantum programs necessitates an effective compilation process. This involves strategically mapping quantum circuits onto the physical qubits of a quantum processor. The qubits' arrangement, or topology, is pivotal to the circuit's performance, a factor that often defies traditional heuristic or manual optimization methods due to its complexity. In this study, we introduce a novel approach leveraging reinforcement learning to dynamically tailor qubit topologies to the unique specifications of individual quantum circuits, guiding algorithm-driven quantum processor topology design for reducing the depth of mapped circuit, which is particularly critical for the output accuracy on noisy quantum processors. Our method marks a significant departure from previous methods that have been constrained to mapping circuits onto a fixed processor topology. Experiments demonstrate that we have achieved notable enhancements in circuit performance, with a minimum of 20\% reduction in circuit depth in 60\% of the cases examined, and a maximum enhancement of up to 46\%. Furthermore, the pronounced benefits of our approach in reducing circuit depth become increasingly evident as the scale of the quantum circuits increases, exhibiting the scalability of our method in terms of problem size. This work advances the co-design of quantum processor architecture and algorithm mapping, offering a promising avenue for future research and development in the field.

Figures (15)

• Figure 1: Comparative between the existing method and our method: (top) Prior research has focused on the development of mapping algorithms for predefined topologies, primarily aimed at allocating qubits in a way that satisfies connectivity requirements. The result of these methodologies is a fixed mapping protocol. (bottom) Our study employs Reinforcement Learning model to suggest an topology that aligns with the circuit's characteristics under the limitations imposed by restricted connectivity. Subsequently, qubits are mapped in a sequential manner instead of a complex mapping algorithms.
• Figure 2: Overview of proposed Qtailor: (1) The agent acquires state from the environment; state are represented by a flattened matrix that denotes the current topology, where $M_{ij} = 1$ indicates that $Q_i$ and $Q_j$ are connected. (2) Subsequently, the agent outputs an action ($a$), that establish an connection between which two qubits. (3) The action is then applied to the topology. (4) Using the action as a key, we query the reward ($r$) from memory, which stores pairs of $\left \langle a,r \right \rangle$. If a match is found, the corresponding reward will be directly provided to the agent, otherwise, an evaluation involving circuit compilation, computation of depth, and gates is conducted. The reward function is then applied based on the depth or gates, and this reward is stored in memory as a pair of $\left \langle a,r \right \rangle$. This process is referred to as reward replay, detailed in Section \ref{['rr-ppo']}. (5) Finally, The agent receives the reward and continues to the subsequent iteration.
• Figure 3: The forces acting between two and three vertex, each vertex undergoes both repulsive and attractive forces from the other vertex, with these forces counterbalancing each other to maintain the stability of vertex positions.
• Figure 4: Workflow of the Force-directed Grid Layout: (a) Acquire an initial force-directed layout using existing method forceLayout. (b) Initialization the grid point around the point, the point are attracted to the nearest surrounding grid point, vertexes determine the nearest grid point via Euclidean distance, followed by occupation. (c) In instances where ${v}_{1}$ and ${v}_3$ share the closest grid point, they both move to that point. However, an increase in the repulsive force between them as they draw closer ensures that they are effectively repelled. (d) Upon occupation of a grid point by a point, the nearest unoccupied grid points is selected as the new target for other points.
• Figure 5: A comparative evaluation involving QTailor and Qiskit. The x-axis represents the circuit size quantified by the number of qubits, while the y-axis denotes the circuit depth after the mapping process.