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Deployment Pipeline from Rockpool to Xylo for Edge Computing

Peng Zhou, Dylan R. Muir

TL;DR

The paper tackles the challenge of deploying Spiking Neural Networks on neuromorphic hardware by introducing a Rockpool–Xylo deployment pipeline that covers network design, graph extraction, hardware mapping, quantization, deployment, and hardware validation. It defines a graph-centric mapping approach (GraphModule/GraphNode) and a Rockpool-driven hardware mapper, enabling both global and per-channel quantization and rigorous hardware configuration validation. The authors demonstrate end-to-end deployment on the Xylo HDK with validation against a bit-precise Xylo simulator (XyloSim), showing accurate hardware dynamics and facilitating energy-efficient edge computing. This workflow enhances reproducibility and scalability for neuromorphic deployments, potentially generalizable to other hardware targets beyond Xylo.

Abstract

Deploying Spiking Neural Networks (SNNs) on the Xylo neuromorphic chip via the Rockpool framework represents a significant advancement in achieving ultra-low-power consumption and high computational efficiency for edge applications. This paper details a novel deployment pipeline, emphasizing the integration of Rockpool's capabilities with Xylo's architecture, and evaluates the system's performance in terms of energy efficiency and accuracy. The unique advantages of the Xylo chip, including its digital spiking architecture and event-driven processing model, are highlighted to demonstrate its suitability for real-time, power-sensitive applications.

Deployment Pipeline from Rockpool to Xylo for Edge Computing

TL;DR

The paper tackles the challenge of deploying Spiking Neural Networks on neuromorphic hardware by introducing a Rockpool–Xylo deployment pipeline that covers network design, graph extraction, hardware mapping, quantization, deployment, and hardware validation. It defines a graph-centric mapping approach (GraphModule/GraphNode) and a Rockpool-driven hardware mapper, enabling both global and per-channel quantization and rigorous hardware configuration validation. The authors demonstrate end-to-end deployment on the Xylo HDK with validation against a bit-precise Xylo simulator (XyloSim), showing accurate hardware dynamics and facilitating energy-efficient edge computing. This workflow enhances reproducibility and scalability for neuromorphic deployments, potentially generalizable to other hardware targets beyond Xylo.

Abstract

Deploying Spiking Neural Networks (SNNs) on the Xylo neuromorphic chip via the Rockpool framework represents a significant advancement in achieving ultra-low-power consumption and high computational efficiency for edge applications. This paper details a novel deployment pipeline, emphasizing the integration of Rockpool's capabilities with Xylo's architecture, and evaluates the system's performance in terms of energy efficiency and accuracy. The unique advantages of the Xylo chip, including its digital spiking architecture and event-driven processing model, are highlighted to demonstrate its suitability for real-time, power-sensitive applications.

Paper Structure

This paper contains 18 sections, 15 figures, 1 table.

Figures (15)

  • Figure 1: Flowchart summarizing the steps from network definition to deployment on the Xylo HDK using Rockpool.rockpool
  • Figure 2: Illustration of a neural network configuration using Sequential and Residual combinators in Rockpool, with both feedforward and recurrent weight architectures.rockpool
  • Figure 3: Illustration of a GraphModule showing its components and connections.
  • Figure 4: Illustration of a GraphNode showing how it acts as a connector within the network.
  • Figure 5: Demonstration of connecting modules using connect_modules() in Rockpool. This function integrates output nodes from one module with the input nodes of another, effectively chaining the computational flow across modules.
  • ...and 10 more figures