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Integrating HW/SW Functionality for Flexible Wireless Radio

Alexander Strachan, Nigel Topham

TL;DR

This work tackles the rigidity–flexibility trade-off in wireless PHY design by introducing a hybrid hardware/software radio architecture that interleaves a partially reconfigurable accelerator pipeline with CPU-driven software processing via interposers. A unified pipeline supports six Zigbee-like PHY variants, enabling rapid retargeting of modulation schemes without a full hardware redesign, and a cycle-accurate gem5+RTL co-simulation evaluates power and performance across configurations. Key findings show that data movement, not processing complexity, dominates power and that with sufficiently large buffers and early software intervention, the system can approach hardware-like performance; best-case power can be within 3% of hardware in certain scenarios, while late-stage software incurs larger penalties. The study provides a practical path toward embedding new modulation standards in existing designs with modest power overhead and demonstrates a robust co-simulation methodology for embedded SoCs integrating hardware accelerators with software control.

Abstract

Current methods of implementing wireless radio typically take one of two forms; either dedicated fixed-function hardware, or pure Software Defined Radio (SDR). Fixed function hardware is efficient, but being specific to each radio standard it lacks flexibility, whereas Software Defined Radio is highly flexible but requires powerful processors to meet real-time performance constraints. This paper presents a hybrid hardware/software approach that aims to combine the flexibility of SDR with the efficiency of dedicated hardware solutions. We evaluate this approach by simulating five variants of the IEEE 802.15.4 protocol, commonly known as Zigbee, and demonstrate the range of performance and power consumption characteristics for different accelerator and software configurations. Across the spectrum of configurations we see power consumption varies from 8% to 38% of a dedicated hardware implementation, and show how the hybrid approach allows a new modulation standard to be retrofitted to an existing design, with only a modest increase in power consumption.

Integrating HW/SW Functionality for Flexible Wireless Radio

TL;DR

This work tackles the rigidity–flexibility trade-off in wireless PHY design by introducing a hybrid hardware/software radio architecture that interleaves a partially reconfigurable accelerator pipeline with CPU-driven software processing via interposers. A unified pipeline supports six Zigbee-like PHY variants, enabling rapid retargeting of modulation schemes without a full hardware redesign, and a cycle-accurate gem5+RTL co-simulation evaluates power and performance across configurations. Key findings show that data movement, not processing complexity, dominates power and that with sufficiently large buffers and early software intervention, the system can approach hardware-like performance; best-case power can be within 3% of hardware in certain scenarios, while late-stage software incurs larger penalties. The study provides a practical path toward embedding new modulation standards in existing designs with modest power overhead and demonstrates a robust co-simulation methodology for embedded SoCs integrating hardware accelerators with software control.

Abstract

Current methods of implementing wireless radio typically take one of two forms; either dedicated fixed-function hardware, or pure Software Defined Radio (SDR). Fixed function hardware is efficient, but being specific to each radio standard it lacks flexibility, whereas Software Defined Radio is highly flexible but requires powerful processors to meet real-time performance constraints. This paper presents a hybrid hardware/software approach that aims to combine the flexibility of SDR with the efficiency of dedicated hardware solutions. We evaluate this approach by simulating five variants of the IEEE 802.15.4 protocol, commonly known as Zigbee, and demonstrate the range of performance and power consumption characteristics for different accelerator and software configurations. Across the spectrum of configurations we see power consumption varies from 8% to 38% of a dedicated hardware implementation, and show how the hybrid approach allows a new modulation standard to be retrofitted to an existing design, with only a modest increase in power consumption.

Paper Structure

This paper contains 15 sections, 13 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Research Aims and Challenges
  3. Accelerator Architecture
  4. Radio Accelerator Pipeline Design
  5. Interposer Design
  6. Software Design
  7. Operation
  8. Results
  9. CPU Power Consumption
  10. CPU Behaviour
  11. Conclusion
  12. Related Work
  13. Research
  14. Industry
  15. Further Work

Figures (13)

  • Figure 1: Overall System Diagram showing accelerator and interposer connections to CPU and memory hierarchy.
  • Figure 2: Radio Accelerator Pipelines for The Chosen 802.15.4 Standards.
  • Figure 3: Unified Reconfigurable Radio Accelerator Pipeline.
  • Figure 4: Block Diagram Showing Interposer Design.
  • Figure 5: Gem5 Simulation Architecture Overview.
  • ...and 8 more figures