Sampling from exponential distributions in the time domain with superparamagnetic tunnel junctions

TL;DR

The work demonstrates a hardware primitive that samples from exponential distributions by measuring the first switching time of a superparamagnetic MTJ in response to a current step, encoding probabilistic delay in the time domain. It validates exponential-distribution behavior with repeated switches and shows practical use in Metropolis-Hastings steps and weighted random sampling via temporal circuits. The approach promises energy- and latency-efficient probabilistic computation but faces device drift and maturation barriers that require further engineering. Overall, this temporal sampling method expands the toolbox for hardware-based probabilistic inference and temporal computing.

Abstract

In the superparamagnetic regime, magnetic tunnel junctions switch between two resistance states due to random thermal fluctuations. The dwell time distribution in each state is exponential. We sample this distribution using a temporal encoding scheme, in which information is encoded in the time at which the device switches between its resistance states. We then develop a circuit element known as a probabilistic delay cell that applies an electrical current step to a superparamagnetic tunnel junction and a temporal measurement circuit that measures the timing of the first switching event. Repeated experiments confirm that these times are exponentially distributed. Temporal processing methods then allow us to digitally compute with these exponentially distributed probabilistic delay cells. We describe how to use these circuits in a Metropolis-Hastings stepper and in a weighted random sampler, both of which are computationally intensive applications that benefit from the efficient generation of exponentially distributed random numbers.

Figures (6)

• Figure 1: Extracting temporal stochasticity with a current step: Panel (a) shows the current flowing through the device as a function of time. Initially, a low current value keeps the device in the parallel state. At a clock edge, a current step is applied across the device, putting it in the superparamagnetic state, causing a switching event after some delay as is shown in panel (b). The time taken for this switching event $t$ is the quantity of interest, and is measured using on-board electronics. Panel (c) shows the experimentally measured exponential distribution of the times of the first arriving switch, as measured with the circuit shown in Fig. \ref{['fig:ckt-diagram']}(a). The slope of the straight line fit to the data determines the empirical mean $\tau = \langle t\rangle$. The error bars are calculated as the square root of the number of entries in each bin. Approximately 10,000 switching events were collected for a current step with a constant amplitude and width. While the statistical uncertainties are smaller at longer times due to the reduced number of counts, they appear larger on the logarithmic scale. The reduced chi-squared statistic for the fit is $\chi^2$ = 1.92, indicating that the statistical variations provide the primary source of uncertainty in the data.
• Figure 2: Onboard timing measurement of a probabilistic delay cell: Panel (a) shows the timing measurement circuit with the signal and reference path culminating in the clocked counter. The stages that comprise the probabilistic delay cell, which latches the first arriving rising edge, are shown in the upper half of the circuit. The cell consists of a transconductance stage, which behaves as a linear voltage-controlled current source, controlled by the voltage difference between the power supply and the function generator voltage. The power supply is $V_{power} = 10~V$, and the transconductance resistor is $R_{TC}$ = 4.9k$~\Omega$. This is followed by a programmable hysteresis stage to eliminate barrier-crossing errors. The hysteresis window is set by the ratio of the feedback resistor ($R_{F1}$ = 50k$~\Omega$) and the digital potentiometer ($R_{HTh1}$ = 1k$~\Omega$) and the input reference voltage ($V_{REF1}$ = 0.54 V). The digital output goes into a latching stage to catch and keep the first arriving rising edge. The reference path, shown in the bottom half of the circuit, consists of another noise removal hysteresis stage, with the feedback resistor $R_{F2}$ = 24.9k$~\Omega$, threshold resistor $R_{HTh2}$ = 100$~\Omega$ and $V_{REF2} = 5.5~V$. This is followed by a set of logic gates that enable the counter when the reference edge arrives and disables it when the latch is activated. Note that this enable signal is active low and is the length of the delay that we are interested in. The circled numbers in panel (b) correspond to the nodes in panel (a), from which experimentally measured time traces are collected and shown.
• Figure 3: Cumulative distribution function (CDF) of switching times: For three current levels (918 µA, 924 µA, 930 µA), the CDF demonstrates the tunable nature of probabilistic delay cells. Higher currents result in faster switching times, and lower currents give longer switching times, illustrating the input current control of the timing distribution of the device. The colored lines represent the data, while the dotted lines represent the theoretical fits to Eq. \ref{['eq:cdf']}. The inset shows the same data as the lowest current level while showing the long-time behavior of the CDF. The deviation from the fit at long time scales is a result of device variability.
• Figure 4: Exponential dependence of mean switching times with current: The figure shows the exponential relationship between current $I$ and mean switching time $\tau$, as in Eq. \ref{['eq:tau_fit']}. Both datasets are collected on the same device on different days with different current ranges. The error bars on the experimental data show single standard deviation uncertainties in the mean.
• Figure 5: Probabilistic sampling with temporal circuits: Panel (a) shows an inhibit gate, a primitive of temporal computing that can used to block rising edge inputs from propagating through them, based on the relative arrival time between two input signals. Input I is the inhibited input, while input B is the blocking input. If input B arrives first, input I is blocked, and output O remains fixed at 0. If input I arrives first, it is allowed to pass through, causing output O to rise to 1. Panel (a) also shows a single transistor implementation of the inhibit gate from tzimpragos2019boosted. Panel (b) shows the simplest version of a circuit that can make Boolean decisions based on a temporal sample from an exponential distribution. A deterministic delay cell (DDC) and a probabilistic delay cell (PDC) are fed into the B (for blocking) and I (for inhibited) inputs of the inhibit gate, shown in panel (b). The output (O) transitions to a Boolean true value if the probabilistic delay cell fires earlier than a deterministic delay value. Panel (c) extends the notion in panel (b) with two cross-coupled probabilistic delay cells that inhibit each other based on the first arriving probabilistic event. This can be used to generate a biased coin flip when the rates of the two probabilistic delay cells are different from each other. Panel (d) extends the two-input circuit from panel (c) into an $n$-input version, where the OR gate selects the first arriving input and blocks the other inputs such that only the first arriving signal makes it to its output. The final one-hot word, determined by the wire (one of $S_A, S_B, S_C$) that transitioned to 1, encodes the result of the random draw. The probability that output $j$ fires first is described by equation \ref{['eq:exponential_clocks']}.