AiEDA: Agentic AI Design Framework for Digital ASIC System Design

TL;DR

This work proposes AiEDA, an agentic AI design framework that orchestrates digital ASIC design from concept to GDSII using LLMs and open-source EDA tools in iterative feedback loops. By integrating retrieval augmented generation, prompt design, and domain-specific refinements, AiEDA aims to raise designer productivity and reduce time-to-fabrication. The authors demonstrate a KWS case study and validate a partial RTL→GDS path on a simple FIFO, while outlining end-to-end development and open-source release plans. If realized at scale, AiEDA could enable rapid exploration and implementation of ASIC designs with reduced cost and complexity, leveraging community-driven toolchains.

Abstract

The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design.

Figures (3)

• Figure 1: Agentic AI workflow involves an iterative process involving one or more LLMs for reasoning, and planning, and one or more external tools to execute actions. The input could be a design specification in natural language, or a behavioral description in an HDL. The output could be HDL, netlist, or a GDS layout.
• Figure 2: Proposed agentic AI design framework for digital ASIC design. The design flow is broadly divided into four parts: 1) Architecture design (shaded orange), 2) RTL design (shaded yellow), 3) Netlist synthesis (shaded red), and 4) Physical design (shaded purple). At each stage, the design is driven by a combination of LLM and appropriate EDA tools operating in a feedback loop.
• Figure 3: Keyword Spotter (KWS) architecture.