Table of Contents
Fetching ...

Omnidirectional shuttling to avoid valley excitations in Si/SiGe quantum wells

Róbert Németh, Vatsal K. Bandaru, Pedro Alves, Merritt P. Losert, Emma Brann, Owen M. Eskandari, Hudaiba Soomro, Avani Vivrekar, M. A. Eriksson, Mark Friesen

TL;DR

This work addresses valley-state excitations that impair conveyor-mode shuttling of electron-spin qubits in Si/SiGe quantum wells due to random alloy disorder. It compares two 2D-capable strategies: a multichannel shuttler allowing tunneling between parallel channels, and a fully 2D clavette-gate shuttler enabling omnidirectional motion, both evaluated with disorder-influenced simulations. Results show that multichannel paused shuttling can achieve high fidelities but scales poorly, whereas 2D shuttling affords high-fidelity operation across a wide parameter window and enables all-to-all plaquette connectivity, pointing to a scalable architecture for intermediate-range qubit coupling. The findings underscore the importance of valley-splitting engineering and detour-path planning to suppress valley excitations, with practical implications for designing large-scale, shuttling-based silicon quantum computers. The proposed architecture integrates qubit plaquettes, quantum interconnects, and on-chip control to address wiring and connectivity challenges in scalable quantum-dot systems.

Abstract

Conveyor-mode shuttling is a key approach for implementing intermediate-range coupling between electron-spin qubits in quantum dots. Initial implementations are encouraging; however, long shuttling trajectories are guaranteed to encounter regions of low conduction-band valley energy splittings, due to the presence of random-alloy disorder in Si/SiGe quantum wells. Here, we theoretically explore two schemes for avoiding valley-state excitations at these valley-splitting minima, by allowing the electrons to detour around them. A multichannel shuttling scheme allows electrons to tunnel between parallel channels, while a two-dimensional (2D) shuttler provides full omnidirectional control. Using simulations, we estimate shuttling fidelities in these two schemes, obtaining a clear preference for the 2D shuttler. Based on such encouraging results, we propose a modular qubit architecture based on 2D shuttling, which enables all-to-all connectivity within qubit plaquettes and high-fidelity communication between different plaquettes.

Omnidirectional shuttling to avoid valley excitations in Si/SiGe quantum wells

TL;DR

This work addresses valley-state excitations that impair conveyor-mode shuttling of electron-spin qubits in Si/SiGe quantum wells due to random alloy disorder. It compares two 2D-capable strategies: a multichannel shuttler allowing tunneling between parallel channels, and a fully 2D clavette-gate shuttler enabling omnidirectional motion, both evaluated with disorder-influenced simulations. Results show that multichannel paused shuttling can achieve high fidelities but scales poorly, whereas 2D shuttling affords high-fidelity operation across a wide parameter window and enables all-to-all plaquette connectivity, pointing to a scalable architecture for intermediate-range qubit coupling. The findings underscore the importance of valley-splitting engineering and detour-path planning to suppress valley excitations, with practical implications for designing large-scale, shuttling-based silicon quantum computers. The proposed architecture integrates qubit plaquettes, quantum interconnects, and on-chip control to address wiring and connectivity challenges in scalable quantum-dot systems.

Abstract

Conveyor-mode shuttling is a key approach for implementing intermediate-range coupling between electron-spin qubits in quantum dots. Initial implementations are encouraging; however, long shuttling trajectories are guaranteed to encounter regions of low conduction-band valley energy splittings, due to the presence of random-alloy disorder in Si/SiGe quantum wells. Here, we theoretically explore two schemes for avoiding valley-state excitations at these valley-splitting minima, by allowing the electrons to detour around them. A multichannel shuttling scheme allows electrons to tunnel between parallel channels, while a two-dimensional (2D) shuttler provides full omnidirectional control. Using simulations, we estimate shuttling fidelities in these two schemes, obtaining a clear preference for the 2D shuttler. Based on such encouraging results, we propose a modular qubit architecture based on 2D shuttling, which enables all-to-all connectivity within qubit plaquettes and high-fidelity communication between different plaquettes.

Paper Structure

This paper contains 7 sections, 48 equations, 4 figures.

Figures (4)

  • Figure 1: Shuttling schemes for avoiding regions of low valley-energy splittings. (a) A conventional single-channel scheme is formed of one shuttling channel, surrounded by screening gates (S$_1$ and S$_2$) that provide limited control of electron motion transverse to the channel. Clavier gates (C) with gate pitch $P$ are formed into unit cells (indicated by shading); sinusoidally varying voltage signals provide a moving potential pocket that can transport electrons along the channel. (b) A multichannel scheme provides greater transverse motion by defining two or more channels. Independent voltage control of the screening gates (S$_1$-S$_3$) allows for control of the energy detuning and tunnel coupling between the channels. (c) A 2D shuttling scheme is defined by pixel-like "clavette’’ gates, formed into a 2D unit cell, with gate pitch $P$ and separation $W$; sinusoidally varying voltage signals now provide omnidirectional control of the moving potential pocket. (d) A typical map of low valley splittings, similar to those calculated in Losert:2023p125405. Single-channel, two-channel, and 2D shuttling geometries provide increasing levels of transverse shift control (dotted lines), $\Delta y$, to avoid regions with low valley splittings. Here, we assume an average valley splitting of ${\bar{E}}_v = 100$ µeV and dot diameter $2l_\text{dot} = 2\sqrt{\hbar^2/m_t E_\text{orb}} \approx 28$ nm (black scale bar), consistent with a lateral confinement energy of $E_\text{orb} = 2$ meV.
  • Figure 2: Multichannel shuttling simulations. (a) A schematic side view of a shuttling device, showing a Si/SiGe quantum well with clavier (C) and screening (S) gates. (b) A schematic illustration of the four-level model used to simulate valley leakage while transferring the qubit from the left channel ($L$) to the right channel ($R$). We include ground ($g$) and excited ($e$) valley states in each channel, and define the detuning $\varepsilon$ and tunnel coupling $t_c$ between the channels. (c) Illustration of a typical modulation schedule for $\varepsilon(\tau)$ and $t_c(\tau)$, for performing a channel transfer. "Paused" protocol (d)-(g): (d) The computed success probability for a transfer, $P_\text{suc}$, as a function of $t_0$ and $\varepsilon_0$. (e) $P_\text{suc}$ as a function of the total transfer period $\tau_\text{tot}$, for the parameter values $\varepsilon_0 = 1000$ µeV (left) and 500µeV (right). Each data point in (d) and (e) corresponds to an average over 10,000 instances of random-alloy disorder. (f) 2D potential-energy (PE) landscapes obtained at two times during the transfer process: $\tau = 0$ (top) and $\tau = \tau_\text{tot}/2$ (bottom). By varying the screening gate voltages, we can tune both $\varepsilon_0$ and $t_0$; for these two simulations we obtain $\varepsilon_0 = 750$ µeV and $t_0=200$ µeV (see Appendix \ref{['app:electrostatics']}), which give a high probability for success, as indicated in (d). (g) 1D linecuts through the electrostatic potential-energy landscapes shown in (f). Here, we include cuts through $x = 0$ for the cases $\tau = 0$ (orange), $\tau = \tau_\text{tot}/2$ (red), and $\tau = \tau_\text{tot}$ (cyan). The detuning between the cyan and orange curves is barely visible at this scale. Inset: a blown-up view of the double-dot potential for the case $\tau = \tau_\text{tot}/2$. At this point, the barrier height between dots along the channel axis (along $\hat{x}$, not shown) is still $>15$ meV. "Moving" protocol (h),(i): (h) Transfer success probabilities in the "correlated" disorder regime, assuming $\varepsilon_0 = 500$ µeV and $t_0 = 100$ µeV, for the cases $v_x = 1$ ms (orange), 5ms (green), and 10ms (blue). (i) Transfer success probabilities obtained in the "uncorrelated" disorder regime, assuming $v_x = 1$ ms and $t_0 = 100$ µeV, for the cases $\varepsilon_0 = 500$ µeV (orange), 1000 µeV (red), 2500 µeV (cyan), and 5000µeV (purple). Each data point in (h) and (i) is averaged over 200 simulations with randomly generated disorder.
  • Figure 3: 2D shuttling simulations. (a) Schematic side view of a shuttling device, showing a Si/SiGe quantum well with top-gate electrodes. For a 2D shuttler, the top ("clavette’’) gates are formed into 2D unit cells, indicated by shading. By applying sinusoidally varying voltages to these gates, we obtain a 2D array of moving potential pockets in the quantum well (orange curve), capable of moving an electron in any direction. The couplings $t_p$ induce tunneling events between neighboring pockets. (b) Electrostatic simulations of the potential energy (PE) in the quantum well. (See Appendix \ref{['app:electrostatics']}.) (c) Orbital confinement energies of the moving potential pockets for motion along directions defined by $x=0$, $y=0$, or $x=y$, showing stable, omnidirectional transport. (Inset shows a blown-up region.) (d) The leakage probability $1-F$ to neighboring pockets, Eq. (\ref{['eq:leakage']}), is determined as a function of shuttling distance $x$, for the case of small tunnel couplings $t_p = 10^{-8}~meV$, which are typical for this system. Simulations include the effects of potential and valley-splitting fluctuations (shown in the inset as shading variations for a typical, randomized landscape), and charge-state collapse (see main text). The total leakage out of the central pocket is plotted as a solid line, while leakage into individual pockets (see inset) is shown as dashed lines. Note the low leakage scale of $10^{-9}$ found here, indicating that pocket leakage should not be a problem under normal operating conditions. (e) The total leakage $1-F$ at a shuttling distance of $x=10~µm$ is plotted as a function of $t_p$, based on simulations averaged over five disorder realizations. Here, we assume a dot radius of $l_\text{dot} = 14~nm$, corresponding to a typical orbital splitting of $E_\text{orb} = 2~meV$. For the simulations in (b)-(e), we set $V_\text{amp} = 100~mV$, $P = 50~nm$, and $W = 5~nm$. (f) Orbital excitation energies $E_\text{orb}$, as a function of sinusoidal voltage amplitude $V_\text{amp}$ [defined in Eq. (\ref{['eq:Vi2D']})], for the indicated gate pitches $P$. A reasonable threshold of $E_\text{orb}=1.5$ meV Langrock:2023p020305 is indicated (black line), above which orbital excitations are strongly suppressed. (g) The tunnel coupling $t_p$ between neighboring potential pockets, as a function of $V_\text{amp}$, for several different $P$ values, using the same color scheme as (f). A reasonable threshold of $t_p=10^{-5}$ meV is indicated (black line), below which we can assume tunneling to nearby pockets is strongly suppressed. (h) The same results as (f) and (g), combined into a contour plot. The optimal operating window is shaded purple, indicating that orbital and pocket leakage can be strongly suppressed over a wide range of parameters.
  • Figure 4: A proposed quantum computing architecture based on 2D shuttling. The top-left shows a schematic illustration of a modular architecture, with similarities to Vandersypen:2017p34, incorporating three distinct technologies: qubit plaquettes (comprised of qubits, readout and control electronics, arranged around the periphery of a 2D shuttler), quantum interconnects (also comprised of 2D shuttlers), and classical control electronics interspersed between the qubit plaquettes. All-to-all connectivity is enabled within a single plaquette, while the quantum interconnects allow electrons to shuttle around regions of low valley splitting. Although the illustration here is schematic, we envision future architectures with higher numbers of qubits, specialized structures for implementing one or two-qubit gate operations, and seamless connections between plaquette shuttlers and interconnects.